em(4): difference between missed_packets and rx_overrun

[hiren panchasara]

This is what we are seeing on em(4) 82574L chipset running stable/10:

dev.em.0.mac_stats.missed_packets: 1441927
dev.em.0.interrupts.rx_overrun: 153

From the datasheet:
http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-controller-datasheet.html

10.2.7.4 Missed Packets Count - MPC (0x04010; R)
Counts the number of missed packets. Packets are missed when the receive
FIFO has insufficient space to store the incoming packet. This could be
caused because of too few buffers allocated, or because there is
insufficient bandwidth on the IO bus. Events setting this counter
cause RXO, the receiver overrun interrupt, to be set. This register
does not increment if receives are not enabled.

10.2.4.1 Interrupt Cause Read Register - ICR (0x000C0; RC/WC)
RXO Receiver Overrun
Set on receive data FIFO overrun. Could be caused either because
there are no available buffers or because PCIe receive bandwidth is
inadequate.

So, first one is a count and another one is an interrupt. Are these 2
related? Both seem to be happen when on card FIFO gets full. We see no
evidence of RX queue on the host being full based on
dev.em.0.mac_stats.recv_no_buff.

Many a times we see missed_packets increasing without rx_overrun
changing.

The spec says there is a 40KB buffer on card which seems to be used by
both RX and TX? Is is split between them for 20KB each? OR is it
possible that when we are doing high rate TX, we use up that buffer and
RX suffers from that?

Any insights would be helpful to understand the problem.

Cheers,
Hiren
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