ar71xx SPI speed

[Patrick Kelsey]

On Thu, Feb 23, 2012 at 1:57 PM, Adrian Chadd <adrian at freebsd.org> wrote:

>
> If you take a look at the source code, IIRC reads are done via the
> hardware but the writes are done via bit banging.
>
> Are you looking at SPI read, SPI write, or a mix of both?
>
>
Yes, the writes are bitbanged out, and on each clock that is generated on
the bus by a bit write, a read bit is clocked in.  At the end of bitbanging
a byte out, the accumulated read bits are retrieved from a register with
one operation.  I'm looking at the SPI bus itself and measuring the clock,
which appears to be limited by the rate at which one can do the series of
register writes involved in bitbanging each byte out.


> You can increase the hardware SPI clock by correct fondling of the
> right registers but I haven't got any spare cycles to go grovelling
> through the AR7100 datasheet at the moment. Sorry. Poke me in a few
> days.
>
>
I have working code that correctly programs the clock divider in
AR71XX_SPI_CTRL.  When programmed for clock rates below about 7 MHz or so,
the observed clock on the bus tracks with what I program in that register.
Divider values that should result in something faster than about 7 MHz
don't actually, I suppose because the SPI unit itself is on some slow
secondary bus, or has internals running on a relatively slow derivative of
the system clock.  Not having a datasheet, one thing I'm wondering is if
there is something configurable in the SoC clock tree that would allow the
SPI unit register accesses to complete more quickly if they are in fact the
limiting factor here.

Thanks,

Patrick