ar71xx SPI speed

[Adrian Chadd]

Hi,

If you take a look at the source code, IIRC reads are done via the
hardware but the writes are done via bit banging.

Are you looking at SPI read, SPI write, or a mix of both?

You can increase the hardware SPI clock by correct fondling of the
right registers but I haven't got any spare cycles to go grovelling
through the AR7100 datasheet at the moment. Sorry. Poke me in a few
days.


Adrian

On 21 February 2012 14:22, Patrick Kelsey <kelsey at ieee.org> wrote:
> Hi,
>
> I've been doing some SPI-related work on an AR7161-based board (MikroTik
> Routerboard RB450G, CPU @ 680 MHz, DDR @ 340 MHz, AHB @ 170 MHz), and I've
> noticed, via both software cyclecount and logic analyzer traces, that the
> SPI bus clock tops out in the neighborhood of 7 MHz or so.  I can get a
> little more performance out of it if I manually unroll/debranch the loop in
> ar71xx_spi_txrx, but not terribly much.  The (closed source) boot loader
> for this board manages something in the neighborhood of 8.5 MHz (perhaps
> due to not going through a bus abstraction layer in its code).  8MHz-ish
> does seem a bit lethargic for an SoC with otherwise fast moving parts, but
> I don't have any technical documentation on which to base a meaningful
> expectation.
>
> I'm wondering if anyone has had any experience with this SPI controller
> that either corroborates or contradicts this apparent speed limit.
>
> Thanks,
> Patrick
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