intpm: add support for AMD SBxxx SMBus controller

[Andriy Gapon]

on 08/09/2009 23:55 John Baldwin said the following:
> 
> Does it have a valid intpin config register?  Maybe '2' means it has a legacy
> INTx PCI interrupt.

Just for future references, conveniently organized links to the specs can be found
here:
http://www.coreboot.org/Datasheets#AMD_SB700.2FSB710.2FSB750


Description of PCI interrupt router implies that there is a dedicated SMBus
interrupt line (internal to the chip, I guess).
>From BIOS Developer's Guide:
> 4.1   PCI IRQ Routing Registers
> The SB700 uses one pair of I/O ports to do the PCI IRQ routing. The ports are at C00h/C01h.
> Address      Register Name          Description
> C00h         PCI_Intr_Index         PCI IRQ Routing Index
>                                     0 – INTA#
>                                     1 – INTB#
>                                     2 – INTC#
>                                     3 – INTD#
>                                     4 – SCI
>                                     5 – SMBus interrupt
>                                     9 – INTE#
>                                     0Ah – INTF#
>                                     0Bh – INTG#
>                                     0Ch – INTH#
> C01h         PCI_Intr_Data          0 ~ 15 : IRQ0 to IRQ15
>                                     IRQ0, 2, 8, 13 are reserved




Register Reference Guide in addition says:
> Pci_Intr_Data register
> Note: If IOXAPIC is enabled, software must make sure interrupts are not re-routed;
> ie, they should all be set to 0.
> When IOXAPIC is enabled, [...] SMBus interrupt is routed to INTIN[20], [...]

I believe that nowadays IOXAPIC would be typically enabled.
I tried to hardwire intpm to use IRQ20 on SB700, but no SMBus interrupt was ever seen.

And, just in case, here is what the spec says about normal PCI interrupt
configuration registers (of the PCI device that hosts SMBus controller):
>      Interrupt Line - R - 8 bits - [PCI_Reg: 3Ch]
> Field Name       Bits      Default                                Description
> Interrupt Line   7:0        00h     This module does not generate interrupt. This register is
>                                     hardcoded to 0.
>      Interrupt Pin – R - 8 bits - [PCI_Reg: 3Dh]
> Field Name       Bits      Default                                Description
> Interrupt Pin    7:0        00h     This register specifies which interrupt pin the device issues.
>                                     This module does not generate interrupt but contains the
>                                     actual interrupt controller. This register is hardcoded to 0.


P.S. sorry if formatting would come up ugly on your side.

-- 
Andriy Gapon