Re: My ARM64 boot just broke (undefined instruction)

> On Feb 2, 2023, at 05:13, Martin Cracauer <cracauer@cons.org> wrote:
> 
> I am getting a new boot panic on 14-current.
> 
> Platform:
> - Apple Mac M1 mini
> - QEMU 7.2.0 to arm64
> - Last working kernel: Jan 25 main-n260242-f5924ad8fde4
> - kern config GENERIC-NODEBUG
> 
> [...]
> generic_timer0: <ARM Generic Timer> irq 34,35,36 on acpi0
> Undefined instruction: d53be228

That opcode disassembles to
  mrs    x8, CNTP_CTL_EL0
The instruction is in function get_ctrl in sys/arm/arm/generic_timer.c.

Three possibilities:

1. Apple didn't implement the CNTP_CTL_EL0 register to spec.
2. qemu does not handle privileged access properly.
3. There is something non-obvious wrong with the change below.  Copying its author Andrew Turner.  You could try reverting it.

commit c57694ce94712ce1fe0341ae51d70446a7dbbfa2
Author: Andrew Turner <andrew@FreeBSD.org>
Date:   Sat Jan 28 17:36:24 2023 +0000

    Disable the arm physical timer when an irq exists
         Some firmware leaves the timers enabled. Ensure they are disabled if
    there are any physical timer interrupt resources to ensure we don't
    receive any unexpected interrupts from them.

diff --git a/sys/arm/arm/generic_timer.c b/sys/arm/arm/generic_timer.c
index 2527af9b9068..0556643032c2 100644
--- a/sys/arm/arm/generic_timer.c
+++ b/sys/arm/arm/generic_timer.c
@@ -521,7 +521,8 @@ arm_tmr_attach(device_t dev)
        if (sc->res[GT_VIRT] != NULL)
                arm_tmr_disable(false);
        /* And the physical */
-       if (sc->physical)
+       if (sc->res[GT_PHYS_SECURE] != NULL ||
+           sc->res[GT_PHYS_NONSECURE] != NULL)
                arm_tmr_disable(true);