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charset="us-ascii" Content-ID: <041EB8DFB63C93468A6CA44631ADB10C@prod.exchangelabs.com> Content-Transfer-Encoding: quoted-printable List-Id: Porting FreeBSD to ARM processors List-Archive: https://lists.freebsd.org/archives/freebsd-arm List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-arm@freebsd.org MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DS7PR01MB7712.prod.exchangelabs.com X-MS-Exchange-CrossTenant-Network-Message-Id: d62a7c83-4edb-40bf-c5cf-08db053622ac X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Feb 2023 15:57:07.0709 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 64afd9ba-0ecf-4acf-bc36-935f6235ba8b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mgm4sXskgb4V9w0bzWG4Jp4giYJYTaEXYUpKKnkEeYLYQpxjHfF4oZOOf2B1uAIX X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR01MB5928 X-OriginatorOrg: mit.edu X-Rspamd-Queue-Id: 4P73N04b6Xz3Nxf X-Spamd-Bar: ---- X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:3, ipnet:18.9.0.0/16, country:US] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-ThisMailContainsUnwantedMimeParts: N > On Feb 2, 2023, at 05:13, Martin Cracauer wrote: >=20 > I am getting a new boot panic on 14-current. >=20 > Platform: > - Apple Mac M1 mini > - QEMU 7.2.0 to arm64 > - Last working kernel: Jan 25 main-n260242-f5924ad8fde4 > - kern config GENERIC-NODEBUG >=20 > [...] > generic_timer0: irq 34,35,36 on acpi0 > Undefined instruction: d53be228 That opcode disassembles to mrs x8, CNTP_CTL_EL0 The instruction is in function get_ctrl in sys/arm/arm/generic_timer.c. Three possibilities: 1. Apple didn't implement the CNTP_CTL_EL0 register to spec. 2. qemu does not handle privileged access properly. 3. There is something non-obvious wrong with the change below. Copying its= author Andrew Turner. You could try reverting it. commit c57694ce94712ce1fe0341ae51d70446a7dbbfa2 Author: Andrew Turner Date: Sat Jan 28 17:36:24 2023 +0000 Disable the arm physical timer when an irq exists Some firmware leaves the timers enabled. Ensure they are disabled = if there are any physical timer interrupt resources to ensure we don't receive any unexpected interrupts from them. diff --git a/sys/arm/arm/generic_timer.c b/sys/arm/arm/generic_timer.c index 2527af9b9068..0556643032c2 100644 --- a/sys/arm/arm/generic_timer.c +++ b/sys/arm/arm/generic_timer.c @@ -521,7 +521,8 @@ arm_tmr_attach(device_t dev) if (sc->res[GT_VIRT] !=3D NULL) arm_tmr_disable(false); /* And the physical */ - if (sc->physical) + if (sc->res[GT_PHYS_SECURE] !=3D NULL || + sc->res[GT_PHYS_NONSECURE] !=3D NULL) arm_tmr_disable(true);