git: b21402d05875 - main - arm64: Update the ID_AA64MMFR0_EL1 fields

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From: Andrew Turner <andrew_at_FreeBSD.org>
Date: Fri, 28 Jul 2023 12:08:02 UTC
The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=b21402d058755f4b33a82fa8024fbf4501f5a218

commit b21402d058755f4b33a82fa8024fbf4501f5a218
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-07-06 12:34:28 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2023-07-28 11:53:01 +0000

    arm64: Update the ID_AA64MMFR0_EL1 fields
    
    While here move to decimal for the _op and _CR definitions to be used
    by a future macro to define the register when the assembler doesn't
    know about it.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D40890
---
 sys/arm64/arm64/identcpu.c | 19 ++++++++++++++++++-
 sys/arm64/include/armreg.h | 35 +++++++++++++++++++++++++----------
 2 files changed, 43 insertions(+), 11 deletions(-)

diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
index 48c5cf44a9b5..1908dc4e21bc 100644
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -935,6 +935,17 @@ static const struct mrs_field id_aa64isar2_fields[] = {
 
 
 /* ID_AA64MMFR0_EL1 */
+static const struct mrs_field_value id_aa64mmfr0_ecv[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL),
+	MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_CNTHCTL, "ECV+CNTHCTL"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr0_fgt[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, FGT, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
 static const struct mrs_field_value id_aa64mmfr0_exs[] = {
 	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
 	MRS_FIELD_VALUE_END,
@@ -944,6 +955,7 @@ static const struct mrs_field_value id_aa64mmfr0_tgran4_2[] = {
 	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
 	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
 	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
+	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -958,11 +970,13 @@ static const struct mrs_field_value id_aa64mmfr0_tgran16_2[] = {
 	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
 	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
 	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
+	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"),
 	MRS_FIELD_VALUE_END,
 };
 
 static const struct mrs_field_value id_aa64mmfr0_tgran4[] = {
-	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL),
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
+	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -973,6 +987,7 @@ static const struct mrs_field_value id_aa64mmfr0_tgran64[] = {
 
 static const struct mrs_field_value id_aa64mmfr0_tgran16[] = {
 	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL),
+	MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -1009,6 +1024,8 @@ static const struct mrs_field_value id_aa64mmfr0_parange[] = {
 };
 
 static const struct mrs_field id_aa64mmfr0_fields[] = {
+	MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_EXACT, id_aa64mmfr0_ecv),
+	MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_EXACT, id_aa64mmfr0_fgt),
 	MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs),
 	MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT,
 	    id_aa64mmfr0_tgran4_2),
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 6ada3649042f..189344a9bc1e 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -804,11 +804,11 @@
 
 /* ID_AA64MMFR0_EL1 */
 #define	ID_AA64MMFR0_EL1		MRS_REG(ID_AA64MMFR0_EL1)
-#define	ID_AA64MMFR0_EL1_op0		0x3
-#define	ID_AA64MMFR0_EL1_op1		0x0
-#define	ID_AA64MMFR0_EL1_CRn		0x0
-#define	ID_AA64MMFR0_EL1_CRm		0x7
-#define	ID_AA64MMFR0_EL1_op2		0x0
+#define	ID_AA64MMFR0_EL1_op0		3
+#define	ID_AA64MMFR0_EL1_op1		0
+#define	ID_AA64MMFR0_EL1_CRn		0
+#define	ID_AA64MMFR0_EL1_CRm		7
+#define	ID_AA64MMFR0_EL1_op2		0
 #define	ID_AA64MMFR0_PARange_SHIFT	0
 #define	ID_AA64MMFR0_PARange_MASK	(UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
 #define	ID_AA64MMFR0_PARange_VAL(x)	((x) & ID_AA64MMFR0_PARange_MASK)
@@ -844,6 +844,7 @@
 #define	ID_AA64MMFR0_TGran16_VAL(x)	((x) & ID_AA64MMFR0_TGran16_MASK)
 #define	 ID_AA64MMFR0_TGran16_NONE	(UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
 #define	 ID_AA64MMFR0_TGran16_IMPL	(UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
+#define	 ID_AA64MMFR0_TGran16_LPA2	(UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT)
 #define	ID_AA64MMFR0_TGran64_SHIFT	24
 #define	ID_AA64MMFR0_TGran64_MASK	(UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 #define	ID_AA64MMFR0_TGran64_VAL(x)	((x) & ID_AA64MMFR0_TGran64_MASK)
@@ -853,6 +854,7 @@
 #define	ID_AA64MMFR0_TGran4_MASK	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 #define	ID_AA64MMFR0_TGran4_VAL(x)	((x) & ID_AA64MMFR0_TGran4_MASK)
 #define	 ID_AA64MMFR0_TGran4_IMPL	(UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
+#define	 ID_AA64MMFR0_TGran4_LPA2	(UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT)
 #define	 ID_AA64MMFR0_TGran4_NONE	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 #define	ID_AA64MMFR0_TGran16_2_SHIFT	32
 #define	ID_AA64MMFR0_TGran16_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
@@ -860,6 +862,7 @@
 #define	 ID_AA64MMFR0_TGran16_2_TGran16	(UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
 #define	 ID_AA64MMFR0_TGran16_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
 #define	 ID_AA64MMFR0_TGran16_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
+#define	 ID_AA64MMFR0_TGran16_2_LPA2	(UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT)
 #define	ID_AA64MMFR0_TGran64_2_SHIFT	36
 #define	ID_AA64MMFR0_TGran64_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
 #define	ID_AA64MMFR0_TGran64_2_VAL(x)	((x) & ID_AA64MMFR0_TGran64_2_MASK)
@@ -872,19 +875,31 @@
 #define	 ID_AA64MMFR0_TGran4_2_TGran4	(UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
 #define	 ID_AA64MMFR0_TGran4_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
 #define	 ID_AA64MMFR0_TGran4_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
+#define	 ID_AA64MMFR0_TGran4_2_LPA2	(UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT)
 #define	ID_AA64MMFR0_ExS_SHIFT		44
 #define	ID_AA64MMFR0_ExS_MASK		(UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
 #define	ID_AA64MMFR0_ExS_VAL(x)		((x) & ID_AA64MMFR0_ExS_MASK)
 #define	 ID_AA64MMFR0_ExS_ALL		(UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
 #define	 ID_AA64MMFR0_ExS_IMPL		(UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
+#define	ID_AA64MMFR0_FGT_SHIFT		56
+#define	ID_AA64MMFR0_FGT_MASK		(UL(0xf) << ID_AA64MMFR0_FGT_SHIFT)
+#define	ID_AA64MMFR0_FGT_VAL(x)		((x) & ID_AA64MMFR0_FGT_MASK)
+#define	 ID_AA64MMFR0_FGT_NONE		(UL(0x0) << ID_AA64MMFR0_FGT_SHIFT)
+#define	 ID_AA64MMFR0_FGT_IMPL		(UL(0x1) << ID_AA64MMFR0_FGT_SHIFT)
+#define	ID_AA64MMFR0_ECV_SHIFT		60
+#define	ID_AA64MMFR0_ECV_MASK		(UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)
+#define	ID_AA64MMFR0_ECV_VAL(x)		((x) & ID_AA64MMFR0_ECV_MASK)
+#define	 ID_AA64MMFR0_ECV_NONE		(UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)
+#define	 ID_AA64MMFR0_ECV_IMPL		(UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)
+#define	 ID_AA64MMFR0_ECV_CNTHCTL	(UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)
 
 /* ID_AA64MMFR1_EL1 */
 #define	ID_AA64MMFR1_EL1		MRS_REG(ID_AA64MMFR1_EL1)
-#define	ID_AA64MMFR1_EL1_op0		0x3
-#define	ID_AA64MMFR1_EL1_op1		0x0
-#define	ID_AA64MMFR1_EL1_CRn		0x0
-#define	ID_AA64MMFR1_EL1_CRm		0x7
-#define	ID_AA64MMFR1_EL1_op2		0x1
+#define	ID_AA64MMFR1_EL1_op0		3
+#define	ID_AA64MMFR1_EL1_op1		0
+#define	ID_AA64MMFR1_EL1_CRn		0
+#define	ID_AA64MMFR1_EL1_CRm		7
+#define	ID_AA64MMFR1_EL1_op2		1
 #define	ID_AA64MMFR1_HAFDBS_SHIFT	0
 #define	ID_AA64MMFR1_HAFDBS_MASK	(UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
 #define	ID_AA64MMFR1_HAFDBS_VAL(x)	((x) & ID_AA64MMFR1_HAFDBS_MASK)