From nobody Fri Jul 28 12:08:02 2023 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4RC5xZ6qG3z4pyQ9; Fri, 28 Jul 2023 12:08:02 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4RC5xZ5ZkLz42jv; Fri, 28 Jul 2023 12:08:02 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1690546082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Jlxz5dl5RyyjRksqhu5YzDuxNOjo9Gp0PKcoxv1yvGs=; b=b981CKxD4LPzsvGbpitO7iGC6fe6qYrsNueKRSBASEXvwDtL1AttYn6uS17gUsJSBBj4dl ZuEY2LXwspkt79+yM5tsNPVCBwlBkniESEx6N0pnsTSEBT/VtD4Fpi4lg8REcz1rFmZ0zn MmjYGwDUjUitVk3eymH/Thfd3bOzmhPzE4WsDwyZcVdq5wz17g8LdES6lS94u+ilvJND0F fQETw26q1ydlo+nXflB+gRh4pR4XAKK8snQdTaaaDD3wwNq288IekYO4hhtlGe4kGDLPnZ qDpwGcxGys4h32D9bXSlSPVgHg5MmOWt0aFEwVN+aFtsSj44GqZ7MrRw+nGQUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1690546082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Jlxz5dl5RyyjRksqhu5YzDuxNOjo9Gp0PKcoxv1yvGs=; b=GiZit3j4odJE0o7yY/FIyZNdEKqxQaQIA3hUvdJuzVza5UPWKPe13WUu2j4R5QCSOxVebs bIYBeyBsIKRDIs2H4Ai/lyPhfqgx3KFryd4SQQJc1124QdzEwb+g6EPr8O5viL7rCulS/2 GSIU/uhVdMBSWHkctTQshElZrcCg3tFgG0QkKzbAGf8LXntZqE9iwXabqcQ0mNj3vxYAJF PgxOz7Awbayo+0ZQZtCugo1fPofIjAc991JoVGeonjmqVirdowyHVy1sEO/voTdf5ht6k/ +wEliTPgLT7cQ/1kp9ih1edhimIUevrVKQr3QIeaJwvp6fzAe/76RUzsH9vztQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1690546082; a=rsa-sha256; cv=none; b=hpwM0PUwYBE6AbhbJJsHga9FYP+cuSKESGgo/FfDy26M2hQFFXUm4LQkaDx3m2ez/kRItT orWjsOQxPWGEmctC+/YLOtPyqSpeV+i0bsUTDJ3XgBze0MJ7/8lKGQLJO0eDKElcufEJN2 EZL34u0esmivmQ6G63qAobA4ywbI3eymBXWXFD3uUX6V4Rb+6k6iduEK6dyx3FIji+H98F fffeujdK1IWD1zx4nxVothqcvD/rzBw+GNPOrb0+FcRmelH5xlijX0Jv1fQOns4x0x+FXt gf8nxnXky+EXKTldiSkkDRjL+5IByeEs5pIfQx692h1UMwxlGGAllOZGccFTvg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4RC5xZ4h4Tzqq7; Fri, 28 Jul 2023 12:08:02 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 36SC82jv062085; Fri, 28 Jul 2023 12:08:02 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 36SC82cb062084; Fri, 28 Jul 2023 12:08:02 GMT (envelope-from git) Date: Fri, 28 Jul 2023 12:08:02 GMT Message-Id: <202307281208.36SC82cb062084@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: b21402d05875 - main - arm64: Update the ID_AA64MMFR0_EL1 fields List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: b21402d058755f4b33a82fa8024fbf4501f5a218 Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=b21402d058755f4b33a82fa8024fbf4501f5a218 commit b21402d058755f4b33a82fa8024fbf4501f5a218 Author: Andrew Turner AuthorDate: 2023-07-06 12:34:28 +0000 Commit: Andrew Turner CommitDate: 2023-07-28 11:53:01 +0000 arm64: Update the ID_AA64MMFR0_EL1 fields While here move to decimal for the _op and _CR definitions to be used by a future macro to define the register when the assembler doesn't know about it. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40890 --- sys/arm64/arm64/identcpu.c | 19 ++++++++++++++++++- sys/arm64/include/armreg.h | 35 +++++++++++++++++++++++++---------- 2 files changed, 43 insertions(+), 11 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 48c5cf44a9b5..1908dc4e21bc 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -935,6 +935,17 @@ static const struct mrs_field id_aa64isar2_fields[] = { /* ID_AA64MMFR0_EL1 */ +static const struct mrs_field_value id_aa64mmfr0_ecv[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_CNTHCTL, "ECV+CNTHCTL"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr0_fgt[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, FGT, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64mmfr0_exs[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL), MRS_FIELD_VALUE_END, @@ -944,6 +955,7 @@ static const struct mrs_field_value id_aa64mmfr0_tgran4_2[] = { MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""), MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"), MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"), + MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"), MRS_FIELD_VALUE_END, }; @@ -958,11 +970,13 @@ static const struct mrs_field_value id_aa64mmfr0_tgran16_2[] = { MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""), MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"), MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"), + MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"), MRS_FIELD_VALUE_END, }; static const struct mrs_field_value id_aa64mmfr0_tgran4[] = { - MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL), + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"), MRS_FIELD_VALUE_END, }; @@ -973,6 +987,7 @@ static const struct mrs_field_value id_aa64mmfr0_tgran64[] = { static const struct mrs_field_value id_aa64mmfr0_tgran16[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"), MRS_FIELD_VALUE_END, }; @@ -1009,6 +1024,8 @@ static const struct mrs_field_value id_aa64mmfr0_parange[] = { }; static const struct mrs_field id_aa64mmfr0_fields[] = { + MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_EXACT, id_aa64mmfr0_ecv), + MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_EXACT, id_aa64mmfr0_fgt), MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs), MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT, id_aa64mmfr0_tgran4_2), diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 6ada3649042f..189344a9bc1e 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -804,11 +804,11 @@ /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) -#define ID_AA64MMFR0_EL1_op0 0x3 -#define ID_AA64MMFR0_EL1_op1 0x0 -#define ID_AA64MMFR0_EL1_CRn 0x0 -#define ID_AA64MMFR0_EL1_CRm 0x7 -#define ID_AA64MMFR0_EL1_op2 0x0 +#define ID_AA64MMFR0_EL1_op0 3 +#define ID_AA64MMFR0_EL1_op1 0 +#define ID_AA64MMFR0_EL1_CRn 0 +#define ID_AA64MMFR0_EL1_CRm 7 +#define ID_AA64MMFR0_EL1_op2 0 #define ID_AA64MMFR0_PARange_SHIFT 0 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) @@ -844,6 +844,7 @@ #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) +#define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT) #define ID_AA64MMFR0_TGran64_SHIFT 24 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) @@ -853,6 +854,7 @@ #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) +#define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT) #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) #define ID_AA64MMFR0_TGran16_2_SHIFT 32 #define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) @@ -860,6 +862,7 @@ #define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) +#define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT) #define ID_AA64MMFR0_TGran64_2_SHIFT 36 #define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) @@ -872,19 +875,31 @@ #define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) +#define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT) #define ID_AA64MMFR0_ExS_SHIFT 44 #define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) #define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) #define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) +#define ID_AA64MMFR0_FGT_SHIFT 56 +#define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT) +#define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK) +#define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT) +#define ID_AA64MMFR0_FGT_IMPL (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT) +#define ID_AA64MMFR0_ECV_SHIFT 60 +#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT) +#define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK) +#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT) +#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT) +#define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT) /* ID_AA64MMFR1_EL1 */ #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) -#define ID_AA64MMFR1_EL1_op0 0x3 -#define ID_AA64MMFR1_EL1_op1 0x0 -#define ID_AA64MMFR1_EL1_CRn 0x0 -#define ID_AA64MMFR1_EL1_CRm 0x7 -#define ID_AA64MMFR1_EL1_op2 0x1 +#define ID_AA64MMFR1_EL1_op0 3 +#define ID_AA64MMFR1_EL1_op1 0 +#define ID_AA64MMFR1_EL1_CRn 0 +#define ID_AA64MMFR1_EL1_CRm 7 +#define ID_AA64MMFR1_EL1_op2 1 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)