git: 1f0174c92786 - main - arm64: Add support for FIQs

The branch main has been updated by imp:

URL: https://cgit.FreeBSD.org/src/commit/?id=1f0174c92786938ee260d973f5c5172b1a4f6435

commit 1f0174c92786938ee260d973f5c5172b1a4f6435
Author:     Ayrton Munoz <a.munoz3327@gmail.com>
AuthorDate: 2024-08-10 15:38:26 +0000
Commit:     Warner Losh <imp@FreeBSD.org>
CommitDate: 2024-09-22 13:18:34 +0000

    arm64: Add support for FIQs
    
    arm64 supports FIQs, fast interrupt requests, which are required by
    Apple silicon which hardwires the ARM timers to FIQs. This is needed by
    the upcoming Apple Interrupt Controller. Based on work by andrew@ and
    kevans@ in https://reviews.freebsd.org/D40161.
    
    Signed-off-by: Ayrton Munoz <a.munoz3327@gmail.com>
    Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
    Co-authored-by: Andrew Turner <andrew@FreeBSD.org>
    Reviewed-by: imp,mmel,mhorne
    Pull-Request: https://github.com/freebsd/freebsd-src/pull/1363
---
 sys/arm64/arm64/exception.S | 32 ++++++++++++++++++++++++++++----
 sys/arm64/include/armreg.h  |  4 ++--
 sys/arm64/include/intr.h    |  6 ++++++
 3 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S
index 9e33fd998502..b3f2a3931e08 100644
--- a/sys/arm64/arm64/exception.S
+++ b/sys/arm64/arm64/exception.S
@@ -30,6 +30,7 @@
 
 #include <machine/asm.h>
 #include <machine/armreg.h>
+#include <machine/intr.h>
 #include "assym.inc"
 
 	.text
@@ -170,7 +171,7 @@
 .macro	do_ast
 	mrs	x19, daif
 	/* Make sure the IRQs are enabled before calling ast() */
-	bic	x19, x19, #PSR_I
+	bic	x19, x19, #(PSR_I | PSR_F)
 1:
 	/*
 	 * Mask interrupts while checking the ast pending flag
@@ -240,6 +241,17 @@ ENTRY(handle_el1h_irq)
 	ERET
 END(handle_el1h_irq)
 
+ENTRY(handle_el1h_fiq)
+	save_registers 1
+	KMSAN_ENTER
+	mov	x0, sp
+	mov	x1, #INTR_ROOT_FIQ
+	bl	intr_irq_handler
+	KMSAN_LEAVE
+	restore_registers 1
+	ERET
+END(handle_el1h_fiq)
+
 ENTRY(handle_el1h_serror)
 	save_registers 1
 	KMSAN_ENTER
@@ -276,6 +288,18 @@ ENTRY(handle_el0_irq)
 	ERET
 END(handle_el0_irq)
 
+ENTRY(handle_el0_fiq)
+	save_registers 0
+	KMSAN_ENTER
+	mov	x0, sp
+	mov	x1, #INTR_ROOT_FIQ
+	bl	intr_irq_handler
+	do_ast
+	KMSAN_LEAVE
+	restore_registers 0
+	ERET
+END(handle_el0_fiq)
+
 ENTRY(handle_el0_serror)
 	save_registers 0
 	KMSAN_ENTER
@@ -318,17 +342,17 @@ exception_vectors:
 
 	vector el1h_sync 1	/* Synchronous EL1h */
 	vector el1h_irq 1	/* IRQ EL1h */
-	vempty 1		/* FIQ EL1h */
+	vector el1h_fiq 1	/* FIQ EL1h */
 	vector el1h_serror 1	/* Error EL1h */
 
 	vector el0_sync 0	/* Synchronous 64-bit EL0 */
 	vector el0_irq 0	/* IRQ 64-bit EL0 */
-	vempty 0		/* FIQ 64-bit EL0 */
+	vector el0_fiq 0	/* FIQ 64-bit EL0 */
 	vector el0_serror 0	/* Error 64-bit EL0 */
 
 	vector el0_sync 0	/* Synchronous 32-bit EL0 */
 	vector el0_irq 0	/* IRQ 32-bit EL0 */
-	vempty 0		/* FIQ 32-bit EL0 */
+	vector el0_fiq 0	/* FIQ 32-bit EL0 */
 	vector el0_serror 0	/* Error 32-bit EL0 */
 
 GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL)
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 54600d63891e..2c4707679432 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -411,7 +411,7 @@
 #define	DAIF_I			(1 << 1)
 #define	DAIF_F			(1 << 0)
 #define	DAIF_ALL		(DAIF_D | DAIF_A | DAIF_I | DAIF_F)
-#define	DAIF_INTR		(DAIF_I)	/* All exceptions that pass */
+#define	DAIF_INTR		(DAIF_I | DAIF_F)	/* All exceptions that pass */
 						/* through the intr framework */
 
 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
@@ -2401,7 +2401,7 @@
 #define	PSR_D		0x00000200UL
 #define	PSR_DAIF	(PSR_D | PSR_A | PSR_I | PSR_F)
 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */
-#define	PSR_DAIF_DEFAULT (PSR_F)
+#define	PSR_DAIF_DEFAULT (0)
 #define	PSR_BTYPE	0x00000c00UL
 #define	PSR_SSBS	0x00001000UL
 #define	PSR_ALLINT	0x00002000UL
diff --git a/sys/arm64/include/intr.h b/sys/arm64/include/intr.h
index 3cdbc83ff109..f7aa2de0ee00 100644
--- a/sys/arm64/include/intr.h
+++ b/sys/arm64/include/intr.h
@@ -27,6 +27,7 @@
 #ifndef _MACHINE_INTR_H_
 #define	_MACHINE_INTR_H_
 
+#ifndef LOCORE
 #ifdef FDT
 #include <dev/ofw/openfirm.h>
 #endif
@@ -48,4 +49,9 @@ arm_irq_memory_barrier(uintptr_t irq)
 #define	ACPI_GPIO_XREF	3
 #endif
 
+#endif	/* !LOCORE */
+
+#define	INTR_ROOT_FIQ	1
+#define	INTR_ROOT_NUM	2
+
 #endif	/* _MACHINE_INTR_H */