svn commit: r317948 - in vendor/llvm/dist: docs examples/Kaleidoscope/BuildingAJIT/Chapter1 examples/Kaleidoscope/BuildingAJIT/Chapter2 examples/Kaleidoscope/BuildingAJIT/Chapter3 examples/Kaleidos...
Dimitry Andric
dim at FreeBSD.org
Mon May 8 17:13:03 UTC 2017
Author: dim
Date: Mon May 8 17:12:57 2017
New Revision: 317948
URL: https://svnweb.freebsd.org/changeset/base/317948
Log:
Vendor import of llvm trunk r302418:
https://llvm.org/svn/llvm-project/llvm/trunk@302418
Added:
vendor/llvm/dist/include/llvm/CodeGen/MIRPrinter.h (contents, props changed)
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/DbiModuleList.h (contents, props changed)
vendor/llvm/dist/lib/DebugInfo/PDB/Native/DbiModuleList.cpp (contents, props changed)
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepIICHVX.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepIICScalar.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepTimingClasses.h (contents, props changed)
vendor/llvm/dist/test/Analysis/ScalarEvolution/ZeroStep.ll
vendor/llvm/dist/test/CodeGen/AArch64/fadd-combines.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/scratch-simple.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/waitcnt-looptest.ll
vendor/llvm/dist/test/CodeGen/ARM/acle-intrinsics-v5.ll
vendor/llvm/dist/test/CodeGen/ARM/acle-intrinsics.ll
vendor/llvm/dist/test/CodeGen/ARM/alloca-align.ll
vendor/llvm/dist/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
vendor/llvm/dist/test/CodeGen/Hexagon/rdf-cover-use.ll
vendor/llvm/dist/test/CodeGen/MIR/X86/auto-successor.mir
vendor/llvm/dist/test/CodeGen/MIR/X86/branch-probabilities.mir
vendor/llvm/dist/test/CodeGen/PowerPC/restore-r30.ll
vendor/llvm/dist/test/CodeGen/SystemZ/copy-physreg-128.ll
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/gep.ll
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/legalize-gep.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/mul-scalar.ll
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/mul-vec.ll
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/select-gep.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/select-mul-vec.mir
vendor/llvm/dist/test/CodeGen/X86/avx2-schedule.ll
vendor/llvm/dist/test/CodeGen/X86/build-vector-128.ll
vendor/llvm/dist/test/CodeGen/X86/build-vector-256.ll
vendor/llvm/dist/test/CodeGen/X86/build-vector-512.ll
vendor/llvm/dist/test/CodeGen/X86/ms-inline-asm-avx512.ll
vendor/llvm/dist/test/CodeGen/X86/pr32907.ll
vendor/llvm/dist/test/CodeGen/X86/regcall-no-plt.ll
vendor/llvm/dist/test/CodeGen/X86/xray-custom-log.ll
vendor/llvm/dist/test/CodeGen/X86/xray-loop-detection.ll
vendor/llvm/dist/test/DebugInfo/COFF/synthetic.ll
vendor/llvm/dist/test/DebugInfo/Inputs/dwarfdump-decompression-error.elf-x86-64 (contents, props changed)
vendor/llvm/dist/test/DebugInfo/dwarfdump-decompression-error.test
vendor/llvm/dist/test/Linker/metadata-global.ll
vendor/llvm/dist/test/MC/AArch64/crc.s (contents, props changed)
vendor/llvm/dist/test/MC/ARM/ltorg-range.s (contents, props changed)
vendor/llvm/dist/test/MC/AsmParser/altmacro_string.s (contents, props changed)
vendor/llvm/dist/test/MC/AsmParser/negative_altmacro_string.s (contents, props changed)
vendor/llvm/dist/test/ObjectYAML/wasm/name_section.yaml
vendor/llvm/dist/test/Transforms/ArgumentPromotion/pr32917.ll
vendor/llvm/dist/test/Transforms/LoopIdiom/unsafe.ll
vendor/llvm/dist/test/tools/llvm-objdump/WebAssembly/
vendor/llvm/dist/test/tools/llvm-objdump/WebAssembly/symbol-table.test
vendor/llvm/dist/test/tools/llvm-readobj/Inputs/resources/
vendor/llvm/dist/test/tools/llvm-readobj/Inputs/resources/cursor_small.bmp (contents, props changed)
vendor/llvm/dist/test/tools/llvm-readobj/Inputs/resources/okay_small.bmp (contents, props changed)
vendor/llvm/dist/test/tools/llvm-readobj/Inputs/resources/test_resource.obj.coff (contents, props changed)
vendor/llvm/dist/test/tools/llvm-readobj/Inputs/resources/test_resource.rc
vendor/llvm/dist/test/tools/llvm-readobj/Inputs/resources/test_resource.res (contents, props changed)
Deleted:
vendor/llvm/dist/lib/CodeGen/MIRPrinter.h
vendor/llvm/dist/lib/Target/AArch64/AArch64AddressTypePromotion.cpp
vendor/llvm/dist/test/CodeGen/AMDGPU/local-stack-slot-bug.ll
vendor/llvm/dist/test/CodeGen/ARM/sat-arith.ll
vendor/llvm/dist/test/CodeGen/MIR/Generic/branch-probabilities.ll
vendor/llvm/dist/test/MC/AArch64/cyclone-crc.s
vendor/llvm/dist/test/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll
Modified:
vendor/llvm/dist/docs/Lexicon.rst
vendor/llvm/dist/docs/MIRLangRef.rst
vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter1/toy.cpp
vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter2/toy.cpp
vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter3/toy.cpp
vendor/llvm/dist/examples/Kaleidoscope/Chapter6/toy.cpp
vendor/llvm/dist/examples/Kaleidoscope/Chapter7/toy.cpp
vendor/llvm/dist/examples/Kaleidoscope/Chapter8/toy.cpp
vendor/llvm/dist/include/llvm/ADT/APInt.h
vendor/llvm/dist/include/llvm/ADT/BitVector.h
vendor/llvm/dist/include/llvm/ADT/SmallBitVector.h
vendor/llvm/dist/include/llvm/Analysis/LoopInfoImpl.h
vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h
vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h
vendor/llvm/dist/include/llvm/Analysis/TargetLibraryInfo.def
vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h
vendor/llvm/dist/include/llvm/CodeGen/FastISel.h
vendor/llvm/dist/include/llvm/CodeGen/FunctionLoweringInfo.h
vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/IRTranslator.h
vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
vendor/llvm/dist/include/llvm/CodeGen/MachineFrameInfo.h
vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h
vendor/llvm/dist/include/llvm/DebugInfo/CodeView/TypeDatabase.h
vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h
vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFFormValue.h
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptor.h
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/DbiStream.h
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/NativeCompilandSymbol.h
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/NativeEnumModules.h
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/RawTypes.h
vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/TpiStream.h
vendor/llvm/dist/include/llvm/ExecutionEngine/Orc/RPCSerialization.h
vendor/llvm/dist/include/llvm/ExecutionEngine/RuntimeDyldChecker.h
vendor/llvm/dist/include/llvm/IR/Attributes.h
vendor/llvm/dist/include/llvm/IR/BasicBlock.h
vendor/llvm/dist/include/llvm/IR/CFG.h
vendor/llvm/dist/include/llvm/IR/CallSite.h
vendor/llvm/dist/include/llvm/IR/CallingConv.h
vendor/llvm/dist/include/llvm/IR/ConstantRange.h
vendor/llvm/dist/include/llvm/IR/DataLayout.h
vendor/llvm/dist/include/llvm/IR/DebugInfo.h
vendor/llvm/dist/include/llvm/IR/Dominators.h
vendor/llvm/dist/include/llvm/IR/Function.h
vendor/llvm/dist/include/llvm/IR/InlineAsm.h
vendor/llvm/dist/include/llvm/IR/InstIterator.h
vendor/llvm/dist/include/llvm/IR/InstrTypes.h
vendor/llvm/dist/include/llvm/IR/Intrinsics.td
vendor/llvm/dist/include/llvm/IR/IntrinsicsARM.td
vendor/llvm/dist/include/llvm/IR/ModuleSummaryIndex.h
vendor/llvm/dist/include/llvm/IR/ModuleSummaryIndexYAML.h
vendor/llvm/dist/include/llvm/MC/ConstantPools.h
vendor/llvm/dist/include/llvm/Object/COFF.h
vendor/llvm/dist/include/llvm/Object/Wasm.h
vendor/llvm/dist/include/llvm/ObjectYAML/WasmYAML.h
vendor/llvm/dist/include/llvm/Support/AArch64TargetParser.def
vendor/llvm/dist/include/llvm/Support/BinaryStreamArray.h
vendor/llvm/dist/include/llvm/Support/COFF.h
vendor/llvm/dist/include/llvm/Support/KnownBits.h
vendor/llvm/dist/include/llvm/Support/MathExtras.h
vendor/llvm/dist/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
vendor/llvm/dist/include/llvm/Target/Target.td
vendor/llvm/dist/include/llvm/Target/TargetOpcodes.def
vendor/llvm/dist/include/llvm/Transforms/Instrumentation.h
vendor/llvm/dist/include/llvm/Transforms/Scalar/Float2Int.h
vendor/llvm/dist/lib/Analysis/ConstantFolding.cpp
vendor/llvm/dist/lib/Analysis/InstructionSimplify.cpp
vendor/llvm/dist/lib/Analysis/LazyValueInfo.cpp
vendor/llvm/dist/lib/Analysis/Lint.cpp
vendor/llvm/dist/lib/Analysis/ModuleSummaryAnalysis.cpp
vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp
vendor/llvm/dist/lib/Analysis/TargetLibraryInfo.cpp
vendor/llvm/dist/lib/Analysis/ValueTracking.cpp
vendor/llvm/dist/lib/Bitcode/Reader/BitcodeReader.cpp
vendor/llvm/dist/lib/Bitcode/Writer/BitcodeWriter.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
vendor/llvm/dist/lib/CodeGen/BranchFolding.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/IRTranslator.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/InstructionSelect.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/Legalizer.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/RegBankSelect.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
vendor/llvm/dist/lib/CodeGen/MIRParser/MIParser.cpp
vendor/llvm/dist/lib/CodeGen/MIRPrinter.cpp
vendor/llvm/dist/lib/CodeGen/MIRPrintingPass.cpp
vendor/llvm/dist/lib/CodeGen/MachineFrameInfo.cpp
vendor/llvm/dist/lib/CodeGen/MachineVerifier.cpp
vendor/llvm/dist/lib/CodeGen/PrologEpilogInserter.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp
vendor/llvm/dist/lib/CodeGen/XRayInstrumentation.cpp
vendor/llvm/dist/lib/DebugInfo/CodeView/TypeDatabase.cpp
vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp
vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFFormValue.cpp
vendor/llvm/dist/lib/DebugInfo/PDB/CMakeLists.txt
vendor/llvm/dist/lib/DebugInfo/PDB/Native/DbiStream.cpp
vendor/llvm/dist/lib/DebugInfo/PDB/Native/NativeCompilandSymbol.cpp
vendor/llvm/dist/lib/DebugInfo/PDB/Native/NativeEnumModules.cpp
vendor/llvm/dist/lib/DebugInfo/PDB/Native/NativeExeSymbol.cpp
vendor/llvm/dist/lib/DebugInfo/PDB/Native/TpiStream.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h
vendor/llvm/dist/lib/Fuzzer/FuzzerLoop.cpp
vendor/llvm/dist/lib/IR/ConstantRange.cpp
vendor/llvm/dist/lib/IR/DataLayout.cpp
vendor/llvm/dist/lib/IR/DebugInfo.cpp
vendor/llvm/dist/lib/IR/Instruction.cpp
vendor/llvm/dist/lib/IR/ModuleSummaryIndex.cpp
vendor/llvm/dist/lib/LTO/LTO.cpp
vendor/llvm/dist/lib/LTO/ThinLTOCodeGenerator.cpp
vendor/llvm/dist/lib/MC/ConstantPools.cpp
vendor/llvm/dist/lib/MC/MCParser/AsmParser.cpp
vendor/llvm/dist/lib/Object/COFFObjectFile.cpp
vendor/llvm/dist/lib/Object/WasmObjectFile.cpp
vendor/llvm/dist/lib/ObjectYAML/WasmYAML.cpp
vendor/llvm/dist/lib/Passes/PassBuilder.cpp
vendor/llvm/dist/lib/Support/APInt.cpp
vendor/llvm/dist/lib/Support/TargetParser.cpp
vendor/llvm/dist/lib/Support/Unix/DynamicLibrary.inc
vendor/llvm/dist/lib/Support/Unix/Path.inc
vendor/llvm/dist/lib/Target/AArch64/AArch64.h
vendor/llvm/dist/lib/Target/AArch64/AArch64.td
vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td
vendor/llvm/dist/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64RegisterBankInfo.h
vendor/llvm/dist/lib/Target/AArch64/AArch64TargetMachine.cpp
vendor/llvm/dist/lib/Target/AArch64/CMakeLists.txt
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
vendor/llvm/dist/lib/Target/AMDGPU/SIFrameLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
vendor/llvm/dist/lib/Target/ARM/ARMBaseRegisterInfo.cpp
vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp
vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.h
vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td
vendor/llvm/dist/lib/Target/ARM/ARMInstrNEON.td
vendor/llvm/dist/lib/Target/ARM/ARMInstrThumb2.td
vendor/llvm/dist/lib/Target/ARM/ARMRegisterBankInfo.cpp
vendor/llvm/dist/lib/Target/ARM/ARMRegisterBankInfo.h
vendor/llvm/dist/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
vendor/llvm/dist/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
vendor/llvm/dist/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepITypes.h
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepITypes.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepInstrFormats.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonDepInstrInfo.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonIICHVX.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonIICScalar.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrFormats.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrFormatsV4.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrFormatsV60.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.h
vendor/llvm/dist/lib/Target/Hexagon/HexagonMachineScheduler.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonPatterns.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonPseudo.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonRegisterInfo.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonSchedule.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonScheduleV4.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonScheduleV55.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonScheduleV60.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonScheduleV62.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonSubtarget.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonSubtarget.h
vendor/llvm/dist/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
vendor/llvm/dist/lib/Target/Hexagon/RDFLiveness.cpp
vendor/llvm/dist/lib/Target/Hexagon/RDFRegisters.cpp
vendor/llvm/dist/lib/Target/Hexagon/RDFRegisters.h
vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.cpp
vendor/llvm/dist/lib/Target/NVPTX/NVPTXISelLowering.cpp
vendor/llvm/dist/lib/Target/NVPTX/NVPTXInstrInfo.td
vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp
vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp
vendor/llvm/dist/lib/Target/Sparc/SparcISelLowering.cpp
vendor/llvm/dist/lib/Target/SystemZ/SystemZInstrInfo.cpp
vendor/llvm/dist/lib/Target/X86/AsmParser/X86AsmParser.cpp
vendor/llvm/dist/lib/Target/X86/AsmParser/X86Operand.h
vendor/llvm/dist/lib/Target/X86/X86AsmPrinter.h
vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp
vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp
vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td
vendor/llvm/dist/lib/Target/X86/X86InstrInfo.td
vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td
vendor/llvm/dist/lib/Target/X86/X86InstructionSelector.cpp
vendor/llvm/dist/lib/Target/X86/X86LegalizerInfo.cpp
vendor/llvm/dist/lib/Target/X86/X86LegalizerInfo.h
vendor/llvm/dist/lib/Target/X86/X86MCInstLower.cpp
vendor/llvm/dist/lib/Target/X86/X86OptimizeLEAs.cpp
vendor/llvm/dist/lib/Target/X86/X86RegisterBankInfo.cpp
vendor/llvm/dist/lib/Target/X86/X86RegisterBankInfo.h
vendor/llvm/dist/lib/Target/X86/X86Subtarget.cpp
vendor/llvm/dist/lib/Target/X86/X86TargetTransformInfo.cpp
vendor/llvm/dist/lib/Target/XCore/XCoreISelLowering.cpp
vendor/llvm/dist/lib/Transforms/IPO/ArgumentPromotion.cpp
vendor/llvm/dist/lib/Transforms/IPO/FunctionImport.cpp
vendor/llvm/dist/lib/Transforms/IPO/LowerTypeTests.cpp
vendor/llvm/dist/lib/Transforms/IPO/WholeProgramDevirt.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineAddSub.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCalls.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstructionCombining.cpp
vendor/llvm/dist/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
vendor/llvm/dist/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
vendor/llvm/dist/lib/Transforms/Scalar/Float2Int.cpp
vendor/llvm/dist/lib/Transforms/Scalar/JumpThreading.cpp
vendor/llvm/dist/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
vendor/llvm/dist/lib/Transforms/Scalar/NewGVN.cpp
vendor/llvm/dist/lib/Transforms/Scalar/TailRecursionElimination.cpp
vendor/llvm/dist/lib/Transforms/Utils/BuildLibCalls.cpp
vendor/llvm/dist/lib/Transforms/Utils/SimplifyCFG.cpp
vendor/llvm/dist/lib/Transforms/Utils/ValueMapper.cpp
vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp
vendor/llvm/dist/test/Analysis/CostModel/X86/bitreverse.ll
vendor/llvm/dist/test/Analysis/CostModel/X86/ctbits-cost.ll
vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
vendor/llvm/dist/test/CodeGen/AArch64/loh.mir
vendor/llvm/dist/test/CodeGen/AArch64/machine-copy-remove.mir
vendor/llvm/dist/test/CodeGen/AArch64/machine-sink-zr.mir
vendor/llvm/dist/test/CodeGen/AArch64/regcoal-physreg.mir
vendor/llvm/dist/test/CodeGen/AArch64/xray-attribute-instrumentation.ll
vendor/llvm/dist/test/CodeGen/AArch64/xray-tail-call-sled.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/detect-dead-lanes.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/fmuladd.f32.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/inserted-wait-states.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/lds-size.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/liveness.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/rename-independent-subregs.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/subreg-intervals.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
vendor/llvm/dist/test/CodeGen/ARM/ARMLoadStoreDBG.mir
vendor/llvm/dist/test/CodeGen/ARM/cmp1-peephole-thumb.mir
vendor/llvm/dist/test/CodeGen/ARM/cmp2-peephole-thumb.mir
vendor/llvm/dist/test/CodeGen/ARM/dbg-range-extension.mir
vendor/llvm/dist/test/CodeGen/ARM/vabs.ll
vendor/llvm/dist/test/CodeGen/ARM/xray-armv6-attribute-instrumentation.ll
vendor/llvm/dist/test/CodeGen/ARM/xray-armv7-attribute-instrumentation.ll
vendor/llvm/dist/test/CodeGen/BPF/dwarfdump.ll
vendor/llvm/dist/test/CodeGen/Hexagon/swp-matmul-bitext.ll
vendor/llvm/dist/test/CodeGen/MIR/X86/successor-basic-blocks.mir
vendor/llvm/dist/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
vendor/llvm/dist/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
vendor/llvm/dist/test/CodeGen/X86/addcarry.ll
vendor/llvm/dist/test/CodeGen/X86/avx-isa-check.ll
vendor/llvm/dist/test/CodeGen/X86/avx1-logical-load-folding.ll
vendor/llvm/dist/test/CodeGen/X86/avx512vl-arith.ll
vendor/llvm/dist/test/CodeGen/X86/branchfolding-undef.mir
vendor/llvm/dist/test/CodeGen/X86/combine-abs.ll
vendor/llvm/dist/test/CodeGen/X86/commuted-blend-mask.ll
vendor/llvm/dist/test/CodeGen/X86/ctpop-combine.ll
vendor/llvm/dist/test/CodeGen/X86/dbg-baseptr.ll
vendor/llvm/dist/test/CodeGen/X86/eflags-copy-expansion.mir
vendor/llvm/dist/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll
vendor/llvm/dist/test/CodeGen/X86/implicit-null-checks.mir
vendor/llvm/dist/test/CodeGen/X86/invalid-liveness.mir
vendor/llvm/dist/test/CodeGen/X86/machine-region-info.mir
vendor/llvm/dist/test/CodeGen/X86/pr27681.mir
vendor/llvm/dist/test/CodeGen/X86/pre-coalesce.mir
vendor/llvm/dist/test/CodeGen/X86/shuffle-vs-trunc-512.ll
vendor/llvm/dist/test/CodeGen/X86/stack-folding-int-avx512.ll
vendor/llvm/dist/test/CodeGen/X86/vec_partial.ll
vendor/llvm/dist/test/CodeGen/X86/vec_reassociate.ll
vendor/llvm/dist/test/CodeGen/X86/vector-lzcnt-512.ll
vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-variable-128.ll
vendor/llvm/dist/test/CodeGen/X86/win64_eh_leaf.ll
vendor/llvm/dist/test/CodeGen/X86/xray-attribute-instrumentation.ll
vendor/llvm/dist/test/CodeGen/X86/xray-tail-call-sled.ll
vendor/llvm/dist/test/MC/AArch64/basic-a64-instructions.s
vendor/llvm/dist/test/MC/AArch64/directive-arch-negative.s
vendor/llvm/dist/test/MC/ARM/negative-immediates-fail.s
vendor/llvm/dist/test/MC/ARM/negative-immediates-thumb1-fail.s
vendor/llvm/dist/test/MC/ARM/negative-immediates.s
vendor/llvm/dist/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
vendor/llvm/dist/test/Other/new-pm-defaults.ll
vendor/llvm/dist/test/Transforms/CodeExtractor/PartialInlineOptRemark.ll
vendor/llvm/dist/test/Transforms/Inline/inline-hot-callsite.ll
vendor/llvm/dist/test/Transforms/Inline/prof-update.ll
vendor/llvm/dist/test/Transforms/InstCombine/AddOverFlow.ll
vendor/llvm/dist/test/Transforms/InstCombine/and-or-icmps.ll
vendor/llvm/dist/test/Transforms/InstCombine/debuginfo-dce.ll
vendor/llvm/dist/test/Transforms/InstCombine/demand_shrink_nsw.ll
vendor/llvm/dist/test/Transforms/InstCombine/or.ll
vendor/llvm/dist/test/Transforms/InstCombine/strlen-1.ll
vendor/llvm/dist/test/Transforms/InstSimplify/AndOrXor.ll
vendor/llvm/dist/test/Transforms/InstSimplify/compare.ll
vendor/llvm/dist/test/Transforms/InstSimplify/icmp-ranges.ll
vendor/llvm/dist/test/Transforms/InstSimplify/shufflevector.ll
vendor/llvm/dist/test/Transforms/LoopRotate/dbgvalue.ll
vendor/llvm/dist/test/Transforms/SampleProfile/Inputs/indirect-call.prof
vendor/llvm/dist/test/Transforms/SampleProfile/indirect-call.ll
vendor/llvm/dist/test/Unit/lit.cfg
vendor/llvm/dist/test/tools/llvm-readobj/resources.test
vendor/llvm/dist/tools/llvm-link/llvm-link.cpp
vendor/llvm/dist/tools/llvm-lto/llvm-lto.cpp
vendor/llvm/dist/tools/llvm-pdbdump/Analyze.cpp
vendor/llvm/dist/tools/llvm-pdbdump/LLVMOutputStyle.cpp
vendor/llvm/dist/tools/llvm-pdbdump/LLVMOutputStyle.h
vendor/llvm/dist/tools/llvm-pdbdump/StreamUtil.cpp
vendor/llvm/dist/tools/llvm-pdbdump/YAMLOutputStyle.cpp
vendor/llvm/dist/tools/llvm-readobj/COFFDumper.cpp
vendor/llvm/dist/tools/llvm-rtdyld/llvm-rtdyld.cpp
vendor/llvm/dist/tools/obj2yaml/wasm2yaml.cpp
vendor/llvm/dist/tools/yaml2obj/yaml2wasm.cpp
vendor/llvm/dist/unittests/ADT/APIntTest.cpp
vendor/llvm/dist/unittests/ADT/BitVectorTest.cpp
vendor/llvm/dist/unittests/Analysis/TargetLibraryInfoTest.cpp
vendor/llvm/dist/unittests/Support/TargetParserTest.cpp
vendor/llvm/dist/utils/release/test-release.sh
vendor/llvm/dist/utils/unittest/googletest/README.LLVM
vendor/llvm/dist/utils/unittest/googletest/include/gtest/internal/gtest-port-arch.h
vendor/llvm/dist/utils/unittest/googletest/include/gtest/internal/gtest-port.h
Modified: vendor/llvm/dist/docs/Lexicon.rst
==============================================================================
--- vendor/llvm/dist/docs/Lexicon.rst Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/docs/Lexicon.rst Mon May 8 17:12:57 2017 (r317948)
@@ -38,6 +38,13 @@ B
**BB Vectorization**
Basic-Block Vectorization
+**BDCE**
+ Bit-tracking dead code elimination. Some bit-wise instructions (shifts,
+ ands, ors, etc.) "kill" some of their input bits -- that is, they make it
+ such that those bits can be either zero or one without affecting control or
+ data flow of a program. The BDCE pass removes instructions that only
+ compute these dead bits.
+
**BURS**
Bottom Up Rewriting System --- A method of instruction selection for code
generation. An example is the `BURG
Modified: vendor/llvm/dist/docs/MIRLangRef.rst
==============================================================================
--- vendor/llvm/dist/docs/MIRLangRef.rst Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/docs/MIRLangRef.rst Mon May 8 17:12:57 2017 (r317948)
@@ -78,6 +78,8 @@ Simplifying MIR files
The MIR code coming out of ``-stop-after``/``-stop-before`` is very verbose;
Tests are more accessible and future proof when simplified:
+- Use the ``-simplify-mir`` option with llc.
+
- Machine function attributes often have default values or the test works just
as well with default values. Typical candidates for this are: `alignment:`,
`exposesReturnsTwice`, `legalized`, `regBankSelected`, `selected`.
Modified: vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter1/toy.cpp
==============================================================================
--- vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter1/toy.cpp Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter1/toy.cpp Mon May 8 17:12:57 2017 (r317948)
@@ -1092,7 +1092,7 @@ Function *FunctionAST::codegen() {
TheFunction->eraseFromParent();
if (P.isBinaryOp())
- BinopPrecedence.erase(Proto->getOperatorName());
+ BinopPrecedence.erase(P.getOperatorName());
return nullptr;
}
Modified: vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter2/toy.cpp
==============================================================================
--- vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter2/toy.cpp Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter2/toy.cpp Mon May 8 17:12:57 2017 (r317948)
@@ -1092,7 +1092,7 @@ Function *FunctionAST::codegen() {
TheFunction->eraseFromParent();
if (P.isBinaryOp())
- BinopPrecedence.erase(Proto->getOperatorName());
+ BinopPrecedence.erase(P.getOperatorName());
return nullptr;
}
Modified: vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter3/toy.cpp
==============================================================================
--- vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter3/toy.cpp Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/examples/Kaleidoscope/BuildingAJIT/Chapter3/toy.cpp Mon May 8 17:12:57 2017 (r317948)
@@ -1092,7 +1092,7 @@ Function *FunctionAST::codegen() {
TheFunction->eraseFromParent();
if (P.isBinaryOp())
- BinopPrecedence.erase(Proto->getOperatorName());
+ BinopPrecedence.erase(P.getOperatorName());
return nullptr;
}
Modified: vendor/llvm/dist/examples/Kaleidoscope/Chapter6/toy.cpp
==============================================================================
--- vendor/llvm/dist/examples/Kaleidoscope/Chapter6/toy.cpp Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/examples/Kaleidoscope/Chapter6/toy.cpp Mon May 8 17:12:57 2017 (r317948)
@@ -932,7 +932,7 @@ Function *FunctionAST::codegen() {
TheFunction->eraseFromParent();
if (P.isBinaryOp())
- BinopPrecedence.erase(Proto->getOperatorName());
+ BinopPrecedence.erase(P.getOperatorName());
return nullptr;
}
Modified: vendor/llvm/dist/examples/Kaleidoscope/Chapter7/toy.cpp
==============================================================================
--- vendor/llvm/dist/examples/Kaleidoscope/Chapter7/toy.cpp Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/examples/Kaleidoscope/Chapter7/toy.cpp Mon May 8 17:12:57 2017 (r317948)
@@ -1099,7 +1099,7 @@ Function *FunctionAST::codegen() {
TheFunction->eraseFromParent();
if (P.isBinaryOp())
- BinopPrecedence.erase(Proto->getOperatorName());
+ BinopPrecedence.erase(P.getOperatorName());
return nullptr;
}
Modified: vendor/llvm/dist/examples/Kaleidoscope/Chapter8/toy.cpp
==============================================================================
--- vendor/llvm/dist/examples/Kaleidoscope/Chapter8/toy.cpp Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/examples/Kaleidoscope/Chapter8/toy.cpp Mon May 8 17:12:57 2017 (r317948)
@@ -1097,7 +1097,7 @@ Function *FunctionAST::codegen() {
TheFunction->eraseFromParent();
if (P.isBinaryOp())
- BinopPrecedence.erase(Proto->getOperatorName());
+ BinopPrecedence.erase(P.getOperatorName());
return nullptr;
}
Modified: vendor/llvm/dist/include/llvm/ADT/APInt.h
==============================================================================
--- vendor/llvm/dist/include/llvm/ADT/APInt.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/ADT/APInt.h Mon May 8 17:12:57 2017 (r317948)
@@ -842,6 +842,7 @@ public:
///
/// \returns *this
APInt &operator*=(const APInt &RHS);
+ APInt &operator*=(uint64_t RHS);
/// \brief Addition assignment operator.
///
@@ -2043,6 +2044,16 @@ inline APInt operator-(uint64_t LHS, API
return b;
}
+inline APInt operator*(APInt a, uint64_t RHS) {
+ a *= RHS;
+ return a;
+}
+
+inline APInt operator*(uint64_t LHS, APInt b) {
+ b *= LHS;
+ return b;
+}
+
namespace APIntOps {
Modified: vendor/llvm/dist/include/llvm/ADT/BitVector.h
==============================================================================
--- vendor/llvm/dist/include/llvm/ADT/BitVector.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/ADT/BitVector.h Mon May 8 17:12:57 2017 (r317948)
@@ -217,7 +217,7 @@ public:
unsigned BitPos = Prev % BITWORD_SIZE;
BitWord Copy = Bits[WordPos];
// Mask off previous bits.
- Copy &= ~0UL << BitPos;
+ Copy &= maskTrailingZeros<BitWord>(BitPos);
if (Copy != 0)
return WordPos * BITWORD_SIZE + countTrailingZeros(Copy);
@@ -229,7 +229,7 @@ public:
return -1;
}
- /// find_next_unset - Returns the index of the next usnet bit following the
+ /// find_next_unset - Returns the index of the next unset bit following the
/// "Prev" bit. Returns -1 if all remaining bits are set.
int find_next_unset(unsigned Prev) const {
++Prev;
@@ -253,7 +253,34 @@ public:
return -1;
}
- /// clear - Clear all bits.
+ /// find_prev - Returns the index of the first set bit that precedes the
+ /// the bit at \p PriorTo. Returns -1 if all previous bits are unset.
+ int find_prev(unsigned PriorTo) {
+ if (PriorTo == 0)
+ return -1;
+
+ --PriorTo;
+
+ unsigned WordPos = PriorTo / BITWORD_SIZE;
+ unsigned BitPos = PriorTo % BITWORD_SIZE;
+ BitWord Copy = Bits[WordPos];
+ // Mask off next bits.
+ Copy &= maskTrailingOnes<BitWord>(BitPos + 1);
+
+ if (Copy != 0)
+ return (WordPos + 1) * BITWORD_SIZE - countLeadingZeros(Copy) - 1;
+
+ // Check previous words.
+ for (unsigned i = 1; i <= WordPos; ++i) {
+ unsigned Index = WordPos - i;
+ if (Bits[Index] == 0)
+ continue;
+ return (Index + 1) * BITWORD_SIZE - countLeadingZeros(Bits[Index]) - 1;
+ }
+ return -1;
+ }
+
+ /// clear - Removes all bits from the bitvector. Does not change capacity.
void clear() {
Size = 0;
}
Modified: vendor/llvm/dist/include/llvm/ADT/SmallBitVector.h
==============================================================================
--- vendor/llvm/dist/include/llvm/ADT/SmallBitVector.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/ADT/SmallBitVector.h Mon May 8 17:12:57 2017 (r317948)
@@ -278,6 +278,24 @@ public:
return getPointer()->find_next_unset(Prev);
}
+ /// find_prev - Returns the index of the first set bit that precedes the
+ /// the bit at \p PriorTo. Returns -1 if all previous bits are unset.
+ int find_prev(unsigned PriorTo) const {
+ if (isSmall()) {
+ if (PriorTo == 0)
+ return -1;
+
+ --PriorTo;
+ uintptr_t Bits = getSmallBits();
+ Bits &= maskTrailingOnes<uintptr_t>(PriorTo + 1);
+ if (Bits == 0)
+ return -1;
+
+ return NumBaseBits - countLeadingZeros(Bits) - 1;
+ }
+ return getPointer()->find_prev(PriorTo);
+ }
+
/// Clear all bits.
void clear() {
if (!isSmall())
Modified: vendor/llvm/dist/include/llvm/Analysis/LoopInfoImpl.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/LoopInfoImpl.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/Analysis/LoopInfoImpl.h Mon May 8 17:12:57 2017 (r317948)
@@ -220,8 +220,8 @@ void LoopBase<BlockT, LoopT>::verifyLoop
BI = df_ext_begin(getHeader(), VisitSet),
BE = df_ext_end(getHeader(), VisitSet);
- // Keep track of the number of BBs visited.
- unsigned NumVisited = 0;
+ // Keep track of the BBs visited.
+ SmallPtrSet<BlockT*, 8> VisitedBBs;
// Check the individual blocks.
for ( ; BI != BE; ++BI) {
@@ -259,10 +259,18 @@ void LoopBase<BlockT, LoopT>::verifyLoop
assert(BB != &getHeader()->getParent()->front() &&
"Loop contains function entry block!");
- NumVisited++;
+ VisitedBBs.insert(BB);
}
- assert(NumVisited == getNumBlocks() && "Unreachable block in loop");
+ if (VisitedBBs.size() != getNumBlocks()) {
+ dbgs() << "The following blocks are unreachable in the loop: ";
+ for (auto BB : Blocks) {
+ if (!VisitedBBs.count(BB)) {
+ dbgs() << *BB << "\n";
+ }
+ }
+ assert(false && "Unreachable block in loop");
+ }
// Check the subloops.
for (iterator I = begin(), E = end(); I != E; ++I)
Modified: vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/Analysis/ProfileSummaryInfo.h Mon May 8 17:12:57 2017 (r317948)
@@ -54,6 +54,18 @@ public:
ProfileSummaryInfo(Module &M) : M(M) {}
ProfileSummaryInfo(ProfileSummaryInfo &&Arg)
: M(Arg.M), Summary(std::move(Arg.Summary)) {}
+
+ /// Handle the invalidation of this information.
+ ///
+ /// When used as a result of \c ProfileSummaryAnalysis this method will be
+ /// called when the module this was computed for changes. Since profile
+ /// summary is immutable after it is annotated on the module, we return false
+ /// here.
+ bool invalidate(Module &, const PreservedAnalyses &,
+ ModuleAnalysisManager::Invalidator &) {
+ return false;
+ }
+
/// Returns the profile count for \p CallInst.
static Optional<uint64_t> getProfileCount(const Instruction *CallInst,
BlockFrequencyInfo *BFI);
Modified: vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h Mon May 8 17:12:57 2017 (r317948)
@@ -782,13 +782,13 @@ private:
/// Set the memoized range for the given SCEV.
const ConstantRange &setRange(const SCEV *S, RangeSignHint Hint,
- const ConstantRange &CR) {
+ ConstantRange &&CR) {
DenseMap<const SCEV *, ConstantRange> &Cache =
Hint == HINT_RANGE_UNSIGNED ? UnsignedRanges : SignedRanges;
- auto Pair = Cache.insert({S, CR});
+ auto Pair = Cache.try_emplace(S, std::move(CR));
if (!Pair.second)
- Pair.first->second = CR;
+ Pair.first->second = std::move(CR);
return Pair.first->second;
}
@@ -816,6 +816,10 @@ private:
/// Helper function called from createNodeForPHI.
const SCEV *createAddRecFromPHI(PHINode *PN);
+ /// A helper function for createAddRecFromPHI to handle simple cases.
+ const SCEV *createSimpleAffineAddRec(PHINode *PN, Value *BEValueV,
+ Value *StartValueV);
+
/// Helper function called from createNodeForPHI.
const SCEV *createNodeFromSelectLikePHI(PHINode *PN);
@@ -1565,7 +1569,7 @@ public:
/// delinearization).
void findArrayDimensions(SmallVectorImpl<const SCEV *> &Terms,
SmallVectorImpl<const SCEV *> &Sizes,
- const SCEV *ElementSize) const;
+ const SCEV *ElementSize);
void print(raw_ostream &OS) const;
void verify() const;
Modified: vendor/llvm/dist/include/llvm/Analysis/TargetLibraryInfo.def
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/TargetLibraryInfo.def Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/Analysis/TargetLibraryInfo.def Mon May 8 17:12:57 2017 (r317948)
@@ -1115,6 +1115,9 @@ TLI_DEFINE_STRING_INTERNAL("vsprintf")
/// int vsscanf(const char *s, const char *format, va_list arg);
TLI_DEFINE_ENUM_INTERNAL(vsscanf)
TLI_DEFINE_STRING_INTERNAL("vsscanf")
+/// size_t wcslen (const wchar_t* wcs);
+TLI_DEFINE_ENUM_INTERNAL(wcslen)
+TLI_DEFINE_STRING_INTERNAL("wcslen")
/// ssize_t write(int fildes, const void *buf, size_t nbyte);
TLI_DEFINE_ENUM_INTERNAL(write)
TLI_DEFINE_STRING_INTERNAL("write")
Modified: vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h Mon May 8 17:12:57 2017 (r317948)
@@ -226,6 +226,7 @@ public:
FUNCTION_EXIT = 1,
TAIL_CALL = 2,
LOG_ARGS_ENTER = 3,
+ CUSTOM_EVENT = 4,
};
// The table will contain these structs that point to the sled, the function
@@ -242,7 +243,7 @@ public:
};
// All the sleds to be emitted.
- std::vector<XRayFunctionEntry> Sleds;
+ SmallVector<XRayFunctionEntry, 4> Sleds;
// Helper function to record a given XRay sled.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind);
Modified: vendor/llvm/dist/include/llvm/CodeGen/FastISel.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/FastISel.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/FastISel.h Mon May 8 17:12:57 2017 (r317948)
@@ -506,6 +506,7 @@ protected:
bool selectCast(const User *I, unsigned Opcode);
bool selectExtractValue(const User *I);
bool selectInsertValue(const User *I);
+ bool selectXRayCustomEvent(const CallInst *II);
private:
/// \brief Handle PHI nodes in successor blocks.
Modified: vendor/llvm/dist/include/llvm/CodeGen/FunctionLoweringInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/FunctionLoweringInfo.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/FunctionLoweringInfo.h Mon May 8 17:12:57 2017 (r317948)
@@ -249,7 +249,7 @@ public:
void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
const KnownBits &Known) {
// Only install this information if it tells us something.
- if (NumSignBits == 1 && Known.Zero == 0 && Known.One == 0)
+ if (NumSignBits == 1 && Known.isUnknown())
return;
LiveOutRegInfo.grow(Reg);
Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/IRTranslator.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/IRTranslator.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/IRTranslator.h Mon May 8 17:12:57 2017 (r317948)
@@ -78,7 +78,7 @@ private:
/// this function.
DenseMap<const AllocaInst *, int> FrameIndices;
- /// Methods for translating form LLVM IR to MachineInstr.
+ /// \name Methods for translating form LLVM IR to MachineInstr.
/// \see ::translate for general information on the translate methods.
/// @{
Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Mon May 8 17:12:57 2017 (r317948)
@@ -45,7 +45,7 @@ class MachineIRBuilder {
/// Debug location to be set to any instruction we create.
DebugLoc DL;
- /// Fields describing the insertion point.
+ /// \name Fields describing the insertion point.
/// @{
MachineBasicBlock *MBB;
MachineBasicBlock::iterator II;
@@ -84,7 +84,7 @@ public:
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
/// @}
- /// Setters for the insertion point.
+ /// \name Setters for the insertion point.
/// @{
/// Set the MachineFunction where to build instructions.
void setMF(MachineFunction &);
@@ -98,7 +98,7 @@ public:
void setInstr(MachineInstr &MI);
/// @}
- /// Control where instructions we create are recorded (typically for
+ /// \name Control where instructions we create are recorded (typically for
/// visiting again later during legalization).
/// @{
void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegBankSelect.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegBankSelect.h Mon May 8 17:12:57 2017 (r317948)
@@ -309,7 +309,7 @@ public:
Impossible
};
- /// Convenient types for a list of insertion points.
+ /// \name Convenient types for a list of insertion points.
/// @{
typedef SmallVector<std::unique_ptr<InsertPoint>, 2> InsertionPoints;
typedef InsertionPoints::iterator insertpt_iterator;
@@ -341,7 +341,7 @@ public:
const TargetRegisterInfo &TRI, Pass &P,
RepairingKind Kind = RepairingKind::Insert);
- /// Getters.
+ /// \name Getters.
/// @{
RepairingKind getKind() const { return Kind; }
unsigned getOpIdx() const { return OpIdx; }
@@ -349,7 +349,7 @@ public:
bool hasSplit() { return HasSplit; }
/// @}
- /// Overloaded methods to add an insertion point.
+ /// \name Overloaded methods to add an insertion point.
/// @{
/// Add a MBBInsertionPoint to the list of InsertPoints.
void addInsertPoint(MachineBasicBlock &MBB, bool Beginning);
@@ -362,7 +362,7 @@ public:
void addInsertPoint(InsertPoint &Point);
/// @}
- /// Accessors related to the insertion points.
+ /// \name Accessors related to the insertion points.
/// @{
insertpt_iterator begin() { return InsertPoints.begin(); }
insertpt_iterator end() { return InsertPoints.end(); }
@@ -561,7 +561,7 @@ private:
/// Find the best mapping for \p MI from \p PossibleMappings.
/// \return a reference on the best mapping in \p PossibleMappings.
- RegisterBankInfo::InstructionMapping &
+ const RegisterBankInfo::InstructionMapping &
findBestMapping(MachineInstr &MI,
RegisterBankInfo::InstructionMappings &PossibleMappings,
SmallVectorImpl<RepairingPlacement> &RepairPts);
Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Mon May 8 17:12:57 2017 (r317948)
@@ -264,7 +264,7 @@ public:
/// Convenient type to represent the alternatives for mapping an
/// instruction.
/// \todo When we move to TableGen this should be an array ref.
- typedef SmallVector<InstructionMapping, 4> InstructionMappings;
+ typedef SmallVector<const InstructionMapping *, 4> InstructionMappings;
/// Helper class used to get/create the virtual registers that will be used
/// to replace the MachineOperand when applying a mapping.
@@ -310,7 +310,7 @@ public:
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
MachineRegisterInfo &MRI);
- /// Getters.
+ /// \name Getters.
/// @{
/// The MachineInstr being remapped.
MachineInstr &getMI() const { return MI; }
@@ -378,15 +378,23 @@ protected:
/// Keep dynamically allocated PartialMapping in a separate map.
/// This shouldn't be needed when everything gets TableGen'ed.
- mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>> MapOfPartialMappings;
+ mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>>
+ MapOfPartialMappings;
/// Keep dynamically allocated ValueMapping in a separate map.
/// This shouldn't be needed when everything gets TableGen'ed.
- mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping> > MapOfValueMappings;
+ mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>>
+ MapOfValueMappings;
/// Keep dynamically allocated array of ValueMapping in a separate map.
/// This shouldn't be needed when everything gets TableGen'ed.
- mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>> MapOfOperandsMappings;
+ mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>>
+ MapOfOperandsMappings;
+
+ /// Keep dynamically allocated InstructionMapping in a separate map.
+ /// This shouldn't be needed when everything gets TableGen'ed.
+ mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>>
+ MapOfInstructionMappings;
/// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks
/// RegisterBank instances.
@@ -425,14 +433,14 @@ protected:
/// register, a register class, or a register bank.
/// In other words, this method will likely fail to find a mapping for
/// any generic opcode that has not been lowered by target specific code.
- InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const;
+ const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
/// Get the uniquely generated PartialMapping for the
/// given arguments.
const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
const RegisterBank &RegBank) const;
- /// Methods to get a uniquely generated ValueMapping.
+ /// \name Methods to get a uniquely generated ValueMapping.
/// @{
/// The most common ValueMapping consists of a single PartialMapping.
@@ -445,7 +453,7 @@ protected:
unsigned NumBreakDowns) const;
/// @}
- /// Methods to get a uniquely generated array of ValueMapping.
+ /// \name Methods to get a uniquely generated array of ValueMapping.
/// @{
/// Get the uniquely generated array of ValueMapping for the
@@ -478,6 +486,33 @@ protected:
std::initializer_list<const ValueMapping *> OpdsMapping) const;
/// @}
+ /// \name Methods to get a uniquely generated InstructionMapping.
+ /// @{
+
+private:
+ /// Method to get a uniquely generated InstructionMapping.
+ const InstructionMapping &
+ getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
+ unsigned Cost = 0,
+ const ValueMapping *OperandsMapping = nullptr,
+ unsigned NumOperands = 0) const;
+
+public:
+ /// Method to get a uniquely generated InstructionMapping.
+ const InstructionMapping &
+ getInstructionMapping(unsigned ID, unsigned Cost,
+ const ValueMapping *OperandsMapping,
+ unsigned NumOperands) const {
+ return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
+ OperandsMapping, NumOperands);
+ }
+
+ /// Method to get a uniquely generated invalid InstructionMapping.
+ const InstructionMapping &getInvalidInstructionMapping() const {
+ return getInstructionMappingImpl(/*IsInvalid*/ true);
+ }
+ /// @}
+
/// Get the register bank for the \p OpIdx-th operand of \p MI form
/// the encoding constraints, if any.
///
@@ -603,7 +638,8 @@ public:
///
/// \note If returnedVal does not verify MI, this would probably mean
/// that the target does not support that instruction.
- virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const;
+ virtual const InstructionMapping &
+ getInstrMapping(const MachineInstr &MI) const;
/// Get the alternative mappings for \p MI.
/// Alternative in the sense different from getInstrMapping.
Added: vendor/llvm/dist/include/llvm/CodeGen/MIRPrinter.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor/llvm/dist/include/llvm/CodeGen/MIRPrinter.h Mon May 8 17:12:57 2017 (r317948)
@@ -0,0 +1,46 @@
+//===- MIRPrinter.h - MIR serialization format printer --------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the functions that print out the LLVM IR and the machine
+// functions using the MIR serialization format.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_CODEGEN_MIRPRINTER_H
+#define LLVM_LIB_CODEGEN_MIRPRINTER_H
+
+namespace llvm {
+
+class MachineBasicBlock;
+class MachineFunction;
+class Module;
+class raw_ostream;
+template <typename T> class SmallVectorImpl;
+
+/// Print LLVM IR using the MIR serialization format to the given output stream.
+void printMIR(raw_ostream &OS, const Module &M);
+
+/// Print a machine function using the MIR serialization format to the given
+/// output stream.
+void printMIR(raw_ostream &OS, const MachineFunction &MF);
+
+/// Determine a possible list of successors of a basic block based on the
+/// basic block machine operand being used inside the block. This should give
+/// you the correct list of successor blocks in most cases except for things
+/// like jump tables where the basic block references can't easily be found.
+/// The MIRPRinter will skip printing successors if they match the result of
+/// this funciton and the parser will use this function to construct a list if
+/// it is missing.
+void guessSuccessors(const MachineBasicBlock &MBB,
+ SmallVectorImpl<MachineBasicBlock*> &Successors,
+ bool &IsFallthrough);
+
+} // end namespace llvm
+
+#endif
Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineFrameInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/MachineFrameInfo.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/MachineFrameInfo.h Mon May 8 17:12:57 2017 (r317948)
@@ -520,6 +520,14 @@ public:
bool hasTailCall() const { return HasTailCall; }
void setHasTailCall() { HasTailCall = true; }
+ /// Computes the maximum size of a callframe and the AdjustsStack property.
+ /// This only works for targets defining
+ /// TargetInstrInfo::getCallFrameSetupOpcode(), getCallFrameDestroyOpcode(),
+ /// and getFrameSize().
+ /// This is usually computed by the prologue epilogue inserter but some
+ /// targets may call this to compute it earlier.
+ void computeMaxCallFrameSize(const MachineFunction &MF);
+
/// Return the maximum size of a call frame that must be
/// allocated for an outgoing function call. This is only available if
/// CallFrameSetup/Destroy pseudo instructions are used by the target, and
Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h Mon May 8 17:12:57 2017 (r317948)
@@ -116,7 +116,7 @@ class MachineModuleInfo : public Immutab
// TODO: Ideally, what we'd like is to have a switch that allows emitting
// synchronous (precise at call-sites only) CFA into .eh_frame. However,
- // even under this switch, we'd like .debug_frame to be precise when using.
+ // even under this switch, we'd like .debug_frame to be precise when using
// -g. At this moment, there's no way to specify that some CFI directives
// go into .eh_frame only, while others go into .debug_frame only.
Modified: vendor/llvm/dist/include/llvm/DebugInfo/CodeView/TypeDatabase.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/CodeView/TypeDatabase.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/DebugInfo/CodeView/TypeDatabase.h Mon May 8 17:12:57 2017 (r317948)
@@ -21,7 +21,7 @@ namespace llvm {
namespace codeview {
class TypeDatabase {
public:
- TypeDatabase() : TypeNameStorage(Allocator) {}
+ explicit TypeDatabase(uint32_t ExpectedSize);
/// Gets the type index for the next type record.
TypeIndex getNextTypeIndex() const;
Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h Mon May 8 17:12:57 2017 (r317948)
@@ -310,6 +310,11 @@ class DWARFContextInMemory : public DWAR
StringRef *MapSectionToMember(StringRef Name);
+ /// If Sec is compressed section, decompresses and updates its contents
+ /// provided by Data. Otherwise leaves it unchanged.
+ Error maybeDecompress(const object::SectionRef &Sec, StringRef Name,
+ StringRef &Data);
+
public:
DWARFContextInMemory(const object::ObjectFile &Obj,
const LoadedObjectInfo *L = nullptr);
Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFFormValue.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFFormValue.h Mon May 8 17:02:03 2017 (r317947)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFFormValue.h Mon May 8 17:12:57 2017 (r317948)
@@ -39,20 +39,18 @@ public:
private:
struct ValueType {
- ValueType() {
- uval = 0;
- }
+ ValueType() { uval = 0; }
union {
uint64_t uval;
int64_t sval;
- const char* cstr;
+ const char *cstr;
};
- const uint8_t* data = nullptr;
+ const uint8_t *data = nullptr;
};
- dwarf::Form Form; // Form for this value.
- ValueType Value; // Contains all data for the form.
+ dwarf::Form Form; // Form for this value.
+ ValueType Value; // Contains all data for the form.
const DWARFUnit *U = nullptr; // Remember the DWARFUnit at extract time.
public:
@@ -84,7 +82,7 @@ public:
const DWARFUnit *U);
bool isInlinedCStr() const {
- return Value.data != nullptr && Value.data == (const uint8_t*)Value.cstr;
+ return Value.data != nullptr && Value.data == (const uint8_t *)Value.cstr;
}
/// getAsFoo functions below return the extracted value as Foo if only
@@ -135,45 +133,45 @@ public:
uint8_t AddrSize,
llvm::dwarf::DwarfFormat Format);
- /// Skip a form in \p debug_info_data at offset specified by \p offset_ptr.
+ /// Skip a form in \p DebugInfoData at offset specified by \p OffsetPtr.
///
/// Skips the bytes for this form in the debug info and updates the offset.
///
- /// \param debug_info_data the .debug_info data to use to skip the value.
- /// \param offset_ptr a reference to the offset that will be updated.
+ /// \param DebugInfoData the .debug_info data to use to skip the value.
+ /// \param OffsetPtr a reference to the offset that will be updated.
/// \param U the DWARFUnit to use when skipping the form in case the form
/// size differs according to data in the DWARFUnit.
/// \returns true on success, false if the form was not skipped.
- bool skipValue(DataExtractor debug_info_data, uint32_t *offset_ptr,
+ bool skipValue(DataExtractor DebugInfoData, uint32_t *OffsetPtr,
const DWARFUnit *U) const;
- /// Skip a form in \p debug_info_data at offset specified by \p offset_ptr.
+ /// Skip a form in \p DebugInfoData at offset specified by \p OffsetPtr.
///
/// Skips the bytes for this form in the debug info and updates the offset.
///
- /// \param form the DW_FORM enumeration that indicates the form to skip.
- /// \param debug_info_data the .debug_info data to use to skip the value.
- /// \param offset_ptr a reference to the offset that will be updated.
+ /// \param Form the DW_FORM enumeration that indicates the form to skip.
+ /// \param DebugInfoData the .debug_info data to use to skip the value.
+ /// \param OffsetPtr a reference to the offset that will be updated.
/// \param U the DWARFUnit to use when skipping the form in case the form
/// size differs according to data in the DWARFUnit.
/// \returns true on success, false if the form was not skipped.
- static bool skipValue(dwarf::Form form, DataExtractor debug_info_data,
- uint32_t *offset_ptr, const DWARFUnit *U);
+ static bool skipValue(dwarf::Form Form, DataExtractor DebugInfoData,
+ uint32_t *OffsetPtr, const DWARFUnit *U);
- /// Skip a form in \p debug_info_data at offset specified by \p offset_ptr.
+ /// Skip a form in \p DebugInfoData at offset specified by \p OffsetPtr.
///
/// Skips the bytes for this form in the debug info and updates the offset.
///
- /// \param form the DW_FORM enumeration that indicates the form to skip.
- /// \param debug_info_data the .debug_info data to use to skip the value.
- /// \param offset_ptr a reference to the offset that will be updated.
+ /// \param Form the DW_FORM enumeration that indicates the form to skip.
+ /// \param DebugInfoData the .debug_info data to use to skip the value.
+ /// \param OffsetPtr a reference to the offset that will be updated.
/// \param Version DWARF version number.
/// \param AddrSize size of an address in bytes.
/// \param Format enum value from llvm::dwarf::DwarfFormat.
/// \returns true on success, false if the form was not skipped.
- static bool skipValue(dwarf::Form form, DataExtractor debug_info_data,
- uint32_t *offset_ptr, uint16_t Version,
- uint8_t AddrSize, llvm::dwarf::DwarfFormat Format);
+ static bool skipValue(dwarf::Form Form, DataExtractor DebugInfoData,
+ uint32_t *OffsetPtr, uint16_t Version, uint8_t AddrSize,
+ llvm::dwarf::DwarfFormat Format);
private:
void dumpString(raw_ostream &OS) const;
@@ -181,149 +179,146 @@ private:
namespace dwarf {
- /// Take an optional DWARFFormValue and try to extract a string value from it.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and was a string.
- inline Optional<const char*> toString(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsCString();
- return None;
- }
-
- /// Take an optional DWARFFormValue and extract a string value from it.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \param Default the default value to return in case of failure.
- /// \returns the string value or Default if the V doesn't have a value or the
- /// form value's encoding wasn't a string.
- inline const char*
- toString(const Optional<DWARFFormValue>& V, const char *Default) {
- return toString(V).getValueOr(Default);
- }
-
- /// Take an optional DWARFFormValue and try to extract an unsigned constant.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and has a unsigned constant form.
- inline Optional<uint64_t> toUnsigned(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsUnsignedConstant();
- return None;
- }
-
- /// Take an optional DWARFFormValue and extract a unsigned constant.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \param Default the default value to return in case of failure.
- /// \returns the extracted unsigned value or Default if the V doesn't have a
- /// value or the form value's encoding wasn't an unsigned constant form.
- inline uint64_t
- toUnsigned(const Optional<DWARFFormValue>& V, uint64_t Default) {
- return toUnsigned(V).getValueOr(Default);
- }
-
- /// Take an optional DWARFFormValue and try to extract an reference.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and has a reference form.
- inline Optional<uint64_t> toReference(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsReference();
- return None;
- }
-
- /// Take an optional DWARFFormValue and extract a reference.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \param Default the default value to return in case of failure.
- /// \returns the extracted reference value or Default if the V doesn't have a
- /// value or the form value's encoding wasn't a reference form.
- inline uint64_t
- toReference(const Optional<DWARFFormValue>& V, uint64_t Default) {
- return toReference(V).getValueOr(Default);
- }
-
- /// Take an optional DWARFFormValue and try to extract an signed constant.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and has a signed constant form.
- inline Optional<int64_t> toSigned(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsSignedConstant();
- return None;
- }
-
- /// Take an optional DWARFFormValue and extract a signed integer.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \param Default the default value to return in case of failure.
- /// \returns the extracted signed integer value or Default if the V doesn't
- /// have a value or the form value's encoding wasn't a signed integer form.
- inline int64_t
- toSigned(const Optional<DWARFFormValue>& V, int64_t Default) {
- return toSigned(V).getValueOr(Default);
- }
-
- /// Take an optional DWARFFormValue and try to extract an address.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and has a address form.
- inline Optional<uint64_t> toAddress(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsAddress();
- return None;
- }
-
- /// Take an optional DWARFFormValue and extract a address.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \param Default the default value to return in case of failure.
- /// \returns the extracted address value or Default if the V doesn't have a
- /// value or the form value's encoding wasn't an address form.
- inline uint64_t
- toAddress(const Optional<DWARFFormValue>& V, uint64_t Default) {
- return toAddress(V).getValueOr(Default);
- }
-
- /// Take an optional DWARFFormValue and try to extract an section offset.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and has a section offset form.
- inline Optional<uint64_t> toSectionOffset(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsSectionOffset();
- return None;
- }
-
- /// Take an optional DWARFFormValue and extract a section offset.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \param Default the default value to return in case of failure.
- /// \returns the extracted section offset value or Default if the V doesn't
- /// have a value or the form value's encoding wasn't a section offset form.
- inline uint64_t
- toSectionOffset(const Optional<DWARFFormValue>& V, uint64_t Default) {
- return toSectionOffset(V).getValueOr(Default);
- }
-
- /// Take an optional DWARFFormValue and try to extract block data.
- ///
- /// \param V and optional DWARFFormValue to attempt to extract the value from.
- /// \returns an optional value that contains a value if the form value
- /// was valid and has a block form.
- inline Optional<ArrayRef<uint8_t>>
- toBlock(const Optional<DWARFFormValue>& V) {
- if (V)
- return V->getAsBlock();
- return None;
- }
+/// Take an optional DWARFFormValue and try to extract a string value from it.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \returns an optional value that contains a value if the form value
+/// was valid and was a string.
+inline Optional<const char *> toString(const Optional<DWARFFormValue> &V) {
+ if (V)
+ return V->getAsCString();
+ return None;
+}
+
+/// Take an optional DWARFFormValue and extract a string value from it.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \param Default the default value to return in case of failure.
+/// \returns the string value or Default if the V doesn't have a value or the
+/// form value's encoding wasn't a string.
+inline const char *toString(const Optional<DWARFFormValue> &V,
+ const char *Default) {
+ return toString(V).getValueOr(Default);
+}
+
+/// Take an optional DWARFFormValue and try to extract an unsigned constant.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \returns an optional value that contains a value if the form value
+/// was valid and has a unsigned constant form.
+inline Optional<uint64_t> toUnsigned(const Optional<DWARFFormValue> &V) {
+ if (V)
+ return V->getAsUnsignedConstant();
+ return None;
+}
+
+/// Take an optional DWARFFormValue and extract a unsigned constant.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \param Default the default value to return in case of failure.
+/// \returns the extracted unsigned value or Default if the V doesn't have a
+/// value or the form value's encoding wasn't an unsigned constant form.
+inline uint64_t toUnsigned(const Optional<DWARFFormValue> &V,
+ uint64_t Default) {
+ return toUnsigned(V).getValueOr(Default);
+}
+
+/// Take an optional DWARFFormValue and try to extract an reference.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \returns an optional value that contains a value if the form value
+/// was valid and has a reference form.
+inline Optional<uint64_t> toReference(const Optional<DWARFFormValue> &V) {
+ if (V)
+ return V->getAsReference();
+ return None;
+}
+
+/// Take an optional DWARFFormValue and extract a reference.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \param Default the default value to return in case of failure.
+/// \returns the extracted reference value or Default if the V doesn't have a
+/// value or the form value's encoding wasn't a reference form.
+inline uint64_t toReference(const Optional<DWARFFormValue> &V,
+ uint64_t Default) {
+ return toReference(V).getValueOr(Default);
+}
+
+/// Take an optional DWARFFormValue and try to extract an signed constant.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \returns an optional value that contains a value if the form value
+/// was valid and has a signed constant form.
+inline Optional<int64_t> toSigned(const Optional<DWARFFormValue> &V) {
+ if (V)
+ return V->getAsSignedConstant();
+ return None;
+}
+
+/// Take an optional DWARFFormValue and extract a signed integer.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \param Default the default value to return in case of failure.
+/// \returns the extracted signed integer value or Default if the V doesn't
+/// have a value or the form value's encoding wasn't a signed integer form.
+inline int64_t toSigned(const Optional<DWARFFormValue> &V, int64_t Default) {
+ return toSigned(V).getValueOr(Default);
+}
+
+/// Take an optional DWARFFormValue and try to extract an address.
+///
+/// \param V and optional DWARFFormValue to attempt to extract the value from.
+/// \returns an optional value that contains a value if the form value
+/// was valid and has a address form.
+inline Optional<uint64_t> toAddress(const Optional<DWARFFormValue> &V) {
+ if (V)
+ return V->getAsAddress();
+ return None;
+}
+
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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