svn commit: r287514 - in vendor/lldb/dist: include/lldb/Core include/lldb/Host/common include/lldb/Target source/Core source/Host/common source/Plugins/Disassembler/llvm source/Plugins/Instruction/...
Dimitry Andric
dim at FreeBSD.org
Sun Sep 6 18:37:25 UTC 2015
Author: dim
Date: Sun Sep 6 18:37:19 2015
New Revision: 287514
URL: https://svnweb.freebsd.org/changeset/base/287514
Log:
Import stripped lldb 3.7.0 release (r246257).
Added:
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContext_mips.h (contents, props changed)
vendor/lldb/dist/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h (contents, props changed)
vendor/lldb/dist/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h (contents, props changed)
Deleted:
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContext_mips64.h
vendor/lldb/dist/source/Plugins/Process/Utility/lldb-mips64-register-enums.h
Modified:
vendor/lldb/dist/include/lldb/Core/ArchSpec.h
vendor/lldb/dist/include/lldb/Host/common/NativeRegisterContext.h
vendor/lldb/dist/include/lldb/Target/StopInfo.h
vendor/lldb/dist/source/Core/ArchSpec.cpp
vendor/lldb/dist/source/Host/common/NativeRegisterContext.cpp
vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h
vendor/lldb/dist/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
vendor/lldb/dist/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.h
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterInfos_mips.h
vendor/lldb/dist/source/Plugins/Process/Utility/RegisterInfos_mips64.h
vendor/lldb/dist/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
vendor/lldb/dist/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
vendor/lldb/dist/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
vendor/lldb/dist/source/Target/StopInfo.cpp
vendor/lldb/dist/tools/lldb-mi/MICmdCmdData.cpp
Modified: vendor/lldb/dist/include/lldb/Core/ArchSpec.h
==============================================================================
--- vendor/lldb/dist/include/lldb/Core/ArchSpec.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/include/lldb/Core/ArchSpec.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -48,7 +48,26 @@ public:
eMIPSSubType_mips64r2el,
eMIPSSubType_mips64r6el,
};
-
+
+ // Masks for the ases word of an ABI flags structure.
+ enum MIPSASE
+ {
+ eMIPSAse_dsp = 0x00000001, // DSP ASE
+ eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE
+ eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme
+ eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE
+ eMIPSAse_mdmx = 0x00000010, // MDMX ASE
+ eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE
+ eMIPSAse_mt = 0x00000040, // MT ASE
+ eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
+ eMIPSAse_virt = 0x00000100, // VZ ASE
+ eMIPSAse_msa = 0x00000200, // MSA ASE
+ eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE
+ eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
+ eMIPSAse_xpa = 0x00001000, // XPA ASE
+ eMIPSAse_mask = 0x00001fff
+ };
+
enum Core
{
eCore_arm_generic,
@@ -546,6 +565,18 @@ public:
StopInfoOverrideCallbackType
GetStopInfoOverrideCallback () const;
+ uint32_t
+ GetFlags () const
+ {
+ return m_flags;
+ }
+
+ void
+ SetFlags (uint32_t flags)
+ {
+ m_flags = flags;
+ }
+
protected:
bool
IsEqualTo (const ArchSpec& rhs, bool exact_match) const;
@@ -554,6 +585,11 @@ protected:
Core m_core;
lldb::ByteOrder m_byte_order;
+ // Additional arch flags which we cannot get from triple and core
+ // For MIPS these are application specific extensions like
+ // micromips, mips16 etc.
+ uint32_t m_flags;
+
ConstString m_distribution_id;
// Called when m_def or m_entry are changed. Fills in all remaining
Modified: vendor/lldb/dist/include/lldb/Host/common/NativeRegisterContext.h
==============================================================================
--- vendor/lldb/dist/include/lldb/Host/common/NativeRegisterContext.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/include/lldb/Host/common/NativeRegisterContext.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -111,6 +111,19 @@ public:
virtual lldb::addr_t
GetWatchpointAddress (uint32_t wp_index);
+ // MIPS Linux kernel returns a masked address (last 3bits are masked)
+ // when a HW watchpoint is hit. However user may not have set a watchpoint
+ // on this address. This function emulates the instruction at PC and
+ // finds the base address used in the load/store instruction. This gives the
+ // exact address used to read/write the variable being watched.
+ // For example:
+ // 'n' is at 0x120010d00 and 'm' is 0x120010d04. When a watchpoint is set at 'm',
+ // then watch exception is generated even when 'n' is read/written. This function
+ // returns address of 'n' so that client can check whether a watchpoint is set
+ // on this address or not.
+ virtual lldb::addr_t
+ GetWatchpointHitAddress (uint32_t wp_index);
+
virtual bool
HardwareSingleStep (bool enable);
Modified: vendor/lldb/dist/include/lldb/Target/StopInfo.h
==============================================================================
--- vendor/lldb/dist/include/lldb/Target/StopInfo.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/include/lldb/Target/StopInfo.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -161,7 +161,7 @@ public:
CreateStopReasonWithBreakpointSiteID (Thread &thread, lldb::break_id_t break_id, bool should_stop);
static lldb::StopInfoSP
- CreateStopReasonWithWatchpointID (Thread &thread, lldb::break_id_t watch_id);
+ CreateStopReasonWithWatchpointID (Thread &thread, lldb::break_id_t watch_id, lldb::addr_t watch_hit_addr = LLDB_INVALID_ADDRESS);
static lldb::StopInfoSP
CreateStopReasonWithSignal (Thread &thread, int signo, const char *description = nullptr);
Modified: vendor/lldb/dist/source/Core/ArchSpec.cpp
==============================================================================
--- vendor/lldb/dist/source/Core/ArchSpec.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Core/ArchSpec.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -90,28 +90,28 @@ static const CoreDefinition g_core_defin
{ eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" },
// mips32, mips32r2, mips32r3, mips32r5, mips32r6
- { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips" },
- { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mipsr2" },
- { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mipsr3" },
- { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mipsr5" },
- { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mipsr6" },
- { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mipsel" },
- { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mipsr2el" },
- { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mipsr3el" },
- { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mipsr5el" },
- { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mipsr6el" },
+ { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips" },
+ { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mipsr2" },
+ { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mipsr3" },
+ { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mipsr5" },
+ { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mipsr6" },
+ { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mipsel" },
+ { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mipsr2el" },
+ { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mipsr3el" },
+ { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mipsr5el" },
+ { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mipsr6el" },
// mips64, mips64r2, mips64r3, mips64r5, mips64r6
- { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
- { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" },
- { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" },
- { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" },
- { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" },
- { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" },
- { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" },
- { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" },
- { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" },
- { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" },
+ { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
+ { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" },
+ { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" },
+ { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" },
+ { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" },
+ { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" },
+ { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" },
+ { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" },
+ { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" },
+ { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" },
{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "powerpc" },
{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
@@ -419,7 +419,8 @@ ArchSpec::ArchSpec() :
m_triple (),
m_core (kCore_invalid),
m_byte_order (eByteOrderInvalid),
- m_distribution_id ()
+ m_distribution_id (),
+ m_flags (0)
{
}
@@ -427,7 +428,8 @@ ArchSpec::ArchSpec (const char *triple_c
m_triple (),
m_core (kCore_invalid),
m_byte_order (eByteOrderInvalid),
- m_distribution_id ()
+ m_distribution_id (),
+ m_flags (0)
{
if (triple_cstr)
SetTriple(triple_cstr, platform);
@@ -438,7 +440,8 @@ ArchSpec::ArchSpec (const char *triple_c
m_triple (),
m_core (kCore_invalid),
m_byte_order (eByteOrderInvalid),
- m_distribution_id ()
+ m_distribution_id (),
+ m_flags (0)
{
if (triple_cstr)
SetTriple(triple_cstr);
@@ -448,7 +451,8 @@ ArchSpec::ArchSpec(const llvm::Triple &t
m_triple (),
m_core (kCore_invalid),
m_byte_order (eByteOrderInvalid),
- m_distribution_id ()
+ m_distribution_id (),
+ m_flags (0)
{
SetTriple(triple);
}
@@ -457,7 +461,8 @@ ArchSpec::ArchSpec (ArchitectureType arc
m_triple (),
m_core (kCore_invalid),
m_byte_order (eByteOrderInvalid),
- m_distribution_id ()
+ m_distribution_id (),
+ m_flags (0)
{
SetArchitecture (arch_type, cpu, subtype);
}
@@ -478,6 +483,7 @@ ArchSpec::operator= (const ArchSpec& rhs
m_core = rhs.m_core;
m_byte_order = rhs.m_byte_order;
m_distribution_id = rhs.m_distribution_id;
+ m_flags = rhs.m_flags;
}
return *this;
}
@@ -489,6 +495,7 @@ ArchSpec::Clear()
m_core = kCore_invalid;
m_byte_order = eByteOrderInvalid;
m_distribution_id.Clear ();
+ m_flags = 0;
}
//===----------------------------------------------------------------------===//
Modified: vendor/lldb/dist/source/Host/common/NativeRegisterContext.cpp
==============================================================================
--- vendor/lldb/dist/source/Host/common/NativeRegisterContext.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Host/common/NativeRegisterContext.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -334,6 +334,12 @@ NativeRegisterContext::GetWatchpointAddr
return LLDB_INVALID_ADDRESS;
}
+lldb::addr_t
+NativeRegisterContext::GetWatchpointHitAddress (uint32_t wp_index)
+{
+ return LLDB_INVALID_ADDRESS;
+}
+
bool
NativeRegisterContext::HardwareSingleStep (bool enable)
{
Modified: vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -415,7 +415,7 @@ protected:
-DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner):
+DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, const char *features_str, unsigned flavor, DisassemblerLLVMC &owner):
m_is_valid(true)
{
std::string Error;
@@ -429,8 +429,6 @@ DisassemblerLLVMC::LLVMCDisassembler::LL
m_instr_info_ap.reset(curr_target->createMCInstrInfo());
m_reg_info_ap.reset (curr_target->createMCRegInfo(triple));
- std::string features_str;
-
m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, cpu,
features_str));
@@ -674,8 +672,25 @@ DisassemblerLLVMC::DisassemblerLLVMC (co
default:
cpu = ""; break;
}
+
+ std::string features_str = "";
+ if (arch.GetTriple().getArch() == llvm::Triple::mips || arch.GetTriple().getArch() == llvm::Triple::mipsel
+ || arch.GetTriple().getArch() == llvm::Triple::mips64 || arch.GetTriple().getArch() == llvm::Triple::mips64el)
+ {
+ uint32_t arch_flags = arch.GetFlags ();
+ if (arch_flags & ArchSpec::eMIPSAse_msa)
+ features_str += "+msa,";
+ if (arch_flags & ArchSpec::eMIPSAse_dsp)
+ features_str += "+dsp,";
+ if (arch_flags & ArchSpec::eMIPSAse_dspr2)
+ features_str += "+dspr2,";
+ if (arch_flags & ArchSpec::eMIPSAse_mips16)
+ features_str += "+mips16,";
+ if (arch_flags & ArchSpec::eMIPSAse_micromips)
+ features_str += "+micromips,";
+ }
- m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this));
+ m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, features_str.c_str(), flavor, *this));
if (!m_disasm_ap->IsValid())
{
// We use m_disasm_ap.get() to tell whether we are valid or not, so if this isn't good for some reason,
@@ -687,7 +702,7 @@ DisassemblerLLVMC::DisassemblerLLVMC (co
if (arch.GetTriple().getArch() == llvm::Triple::arm)
{
std::string thumb_triple(thumb_arch.GetTriple().getTriple());
- m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", flavor, *this));
+ m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", "", flavor, *this));
if (!m_alternate_disasm_ap->IsValid())
{
m_disasm_ap.reset();
Modified: vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h
==============================================================================
--- vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -41,7 +41,7 @@ class DisassemblerLLVMC : public lldb_pr
class LLVMCDisassembler
{
public:
- LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner);
+ LLVMCDisassembler (const char *triple, const char *cpu, const char *features_str, unsigned flavor, DisassemblerLLVMC &owner);
~LLVMCDisassembler();
Modified: vendor/lldb/dist/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -33,7 +33,7 @@
#include "llvm/ADT/STLExtras.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
-#include "Plugins/Process/Utility/RegisterContext_mips64.h" //mips32 has same registers nos as mips64
+#include "Plugins/Process/Utility/RegisterContext_mips.h" //mips32 has same registers nos as mips64
using namespace lldb;
using namespace lldb_private;
@@ -124,6 +124,19 @@ EmulateInstructionMIPS::EmulateInstructi
cpu = "generic"; break;
}
+ std::string features = "";
+ uint32_t arch_flags = arch.GetFlags ();
+ if (arch_flags & ArchSpec::eMIPSAse_msa)
+ features += "+msa,";
+ if (arch_flags & ArchSpec::eMIPSAse_dsp)
+ features += "+dsp,";
+ if (arch_flags & ArchSpec::eMIPSAse_dspr2)
+ features += "+dspr2,";
+ if (arch_flags & ArchSpec::eMIPSAse_mips16)
+ features += "+mips16,";
+ if (arch_flags & ArchSpec::eMIPSAse_micromips)
+ features += "+micromips,";
+
m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
assert (m_reg_info.get());
@@ -131,7 +144,7 @@ EmulateInstructionMIPS::EmulateInstructi
assert (m_insn_info.get());
m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
- m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, ""));
+ m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features));
assert (m_asm_info.get() && m_subtype_info.get());
m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
@@ -289,38 +302,38 @@ EmulateInstructionMIPS::GetRegisterName
case gcc_dwarf_bad_mips: return "bad";
case gcc_dwarf_cause_mips: return "cause";
case gcc_dwarf_pc_mips: return "pc";
- case gcc_dwarf_f0_mips: return "fp_reg[0]";
- case gcc_dwarf_f1_mips: return "fp_reg[1]";
- case gcc_dwarf_f2_mips: return "fp_reg[2]";
- case gcc_dwarf_f3_mips: return "fp_reg[3]";
- case gcc_dwarf_f4_mips: return "fp_reg[4]";
- case gcc_dwarf_f5_mips: return "fp_reg[5]";
- case gcc_dwarf_f6_mips: return "fp_reg[6]";
- case gcc_dwarf_f7_mips: return "fp_reg[7]";
- case gcc_dwarf_f8_mips: return "fp_reg[8]";
- case gcc_dwarf_f9_mips: return "fp_reg[9]";
- case gcc_dwarf_f10_mips: return "fp_reg[10]";
- case gcc_dwarf_f11_mips: return "fp_reg[11]";
- case gcc_dwarf_f12_mips: return "fp_reg[12]";
- case gcc_dwarf_f13_mips: return "fp_reg[13]";
- case gcc_dwarf_f14_mips: return "fp_reg[14]";
- case gcc_dwarf_f15_mips: return "fp_reg[15]";
- case gcc_dwarf_f16_mips: return "fp_reg[16]";
- case gcc_dwarf_f17_mips: return "fp_reg[17]";
- case gcc_dwarf_f18_mips: return "fp_reg[18]";
- case gcc_dwarf_f19_mips: return "fp_reg[19]";
- case gcc_dwarf_f20_mips: return "fp_reg[20]";
- case gcc_dwarf_f21_mips: return "fp_reg[21]";
- case gcc_dwarf_f22_mips: return "fp_reg[22]";
- case gcc_dwarf_f23_mips: return "fp_reg[23]";
- case gcc_dwarf_f24_mips: return "fp_reg[24]";
- case gcc_dwarf_f25_mips: return "fp_reg[25]";
- case gcc_dwarf_f26_mips: return "fp_reg[26]";
- case gcc_dwarf_f27_mips: return "fp_reg[27]";
- case gcc_dwarf_f28_mips: return "fp_reg[28]";
- case gcc_dwarf_f29_mips: return "fp_reg[29]";
- case gcc_dwarf_f30_mips: return "fp_reg[30]";
- case gcc_dwarf_f31_mips: return "fp_reg[31]";
+ case gcc_dwarf_f0_mips: return "f0";
+ case gcc_dwarf_f1_mips: return "f1";
+ case gcc_dwarf_f2_mips: return "f2";
+ case gcc_dwarf_f3_mips: return "f3";
+ case gcc_dwarf_f4_mips: return "f4";
+ case gcc_dwarf_f5_mips: return "f5";
+ case gcc_dwarf_f6_mips: return "f6";
+ case gcc_dwarf_f7_mips: return "f7";
+ case gcc_dwarf_f8_mips: return "f8";
+ case gcc_dwarf_f9_mips: return "f9";
+ case gcc_dwarf_f10_mips: return "f10";
+ case gcc_dwarf_f11_mips: return "f11";
+ case gcc_dwarf_f12_mips: return "f12";
+ case gcc_dwarf_f13_mips: return "f13";
+ case gcc_dwarf_f14_mips: return "f14";
+ case gcc_dwarf_f15_mips: return "f15";
+ case gcc_dwarf_f16_mips: return "f16";
+ case gcc_dwarf_f17_mips: return "f17";
+ case gcc_dwarf_f18_mips: return "f18";
+ case gcc_dwarf_f19_mips: return "f19";
+ case gcc_dwarf_f20_mips: return "f20";
+ case gcc_dwarf_f21_mips: return "f21";
+ case gcc_dwarf_f22_mips: return "f22";
+ case gcc_dwarf_f23_mips: return "f23";
+ case gcc_dwarf_f24_mips: return "f24";
+ case gcc_dwarf_f25_mips: return "f25";
+ case gcc_dwarf_f26_mips: return "f26";
+ case gcc_dwarf_f27_mips: return "f27";
+ case gcc_dwarf_f28_mips: return "f28";
+ case gcc_dwarf_f29_mips: return "f29";
+ case gcc_dwarf_f30_mips: return "f30";
+ case gcc_dwarf_f31_mips: return "f31";
case gcc_dwarf_fcsr_mips: return "fcsr";
case gcc_dwarf_fir_mips: return "fir";
}
Modified: vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -33,7 +33,7 @@
#include "llvm/ADT/STLExtras.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
-#include "Plugins/Process/Utility/RegisterContext_mips64.h"
+#include "Plugins/Process/Utility/RegisterContext_mips.h"
using namespace lldb;
using namespace lldb_private;
@@ -124,6 +124,19 @@ EmulateInstructionMIPS64::EmulateInstruc
cpu = "generic"; break;
}
+ std::string features = "";
+ uint32_t arch_flags = arch.GetFlags ();
+ if (arch_flags & ArchSpec::eMIPSAse_msa)
+ features += "+msa,";
+ if (arch_flags & ArchSpec::eMIPSAse_dsp)
+ features += "+dsp,";
+ if (arch_flags & ArchSpec::eMIPSAse_dspr2)
+ features += "+dspr2,";
+ if (arch_flags & ArchSpec::eMIPSAse_mips16)
+ features += "+mips16,";
+ if (arch_flags & ArchSpec::eMIPSAse_micromips)
+ features += "+micromips,";
+
m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
assert (m_reg_info.get());
@@ -131,7 +144,7 @@ EmulateInstructionMIPS64::EmulateInstruc
assert (m_insn_info.get());
m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
- m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, ""));
+ m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features));
assert (m_asm_info.get() && m_subtype_info.get());
m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
@@ -289,38 +302,38 @@ EmulateInstructionMIPS64::GetRegisterNam
case gcc_dwarf_bad_mips64: return "bad";
case gcc_dwarf_cause_mips64: return "cause";
case gcc_dwarf_pc_mips64: return "pc";
- case gcc_dwarf_f0_mips64: return "fp_reg[0]";
- case gcc_dwarf_f1_mips64: return "fp_reg[1]";
- case gcc_dwarf_f2_mips64: return "fp_reg[2]";
- case gcc_dwarf_f3_mips64: return "fp_reg[3]";
- case gcc_dwarf_f4_mips64: return "fp_reg[4]";
- case gcc_dwarf_f5_mips64: return "fp_reg[5]";
- case gcc_dwarf_f6_mips64: return "fp_reg[6]";
- case gcc_dwarf_f7_mips64: return "fp_reg[7]";
- case gcc_dwarf_f8_mips64: return "fp_reg[8]";
- case gcc_dwarf_f9_mips64: return "fp_reg[9]";
- case gcc_dwarf_f10_mips64: return "fp_reg[10]";
- case gcc_dwarf_f11_mips64: return "fp_reg[11]";
- case gcc_dwarf_f12_mips64: return "fp_reg[12]";
- case gcc_dwarf_f13_mips64: return "fp_reg[13]";
- case gcc_dwarf_f14_mips64: return "fp_reg[14]";
- case gcc_dwarf_f15_mips64: return "fp_reg[15]";
- case gcc_dwarf_f16_mips64: return "fp_reg[16]";
- case gcc_dwarf_f17_mips64: return "fp_reg[17]";
- case gcc_dwarf_f18_mips64: return "fp_reg[18]";
- case gcc_dwarf_f19_mips64: return "fp_reg[19]";
- case gcc_dwarf_f20_mips64: return "fp_reg[20]";
- case gcc_dwarf_f21_mips64: return "fp_reg[21]";
- case gcc_dwarf_f22_mips64: return "fp_reg[22]";
- case gcc_dwarf_f23_mips64: return "fp_reg[23]";
- case gcc_dwarf_f24_mips64: return "fp_reg[24]";
- case gcc_dwarf_f25_mips64: return "fp_reg[25]";
- case gcc_dwarf_f26_mips64: return "fp_reg[26]";
- case gcc_dwarf_f27_mips64: return "fp_reg[27]";
- case gcc_dwarf_f28_mips64: return "fp_reg[28]";
- case gcc_dwarf_f29_mips64: return "fp_reg[29]";
- case gcc_dwarf_f30_mips64: return "fp_reg[30]";
- case gcc_dwarf_f31_mips64: return "fp_reg[31]";
+ case gcc_dwarf_f0_mips64: return "f0";
+ case gcc_dwarf_f1_mips64: return "f1";
+ case gcc_dwarf_f2_mips64: return "f2";
+ case gcc_dwarf_f3_mips64: return "f3";
+ case gcc_dwarf_f4_mips64: return "f4";
+ case gcc_dwarf_f5_mips64: return "f5";
+ case gcc_dwarf_f6_mips64: return "f6";
+ case gcc_dwarf_f7_mips64: return "f7";
+ case gcc_dwarf_f8_mips64: return "f8";
+ case gcc_dwarf_f9_mips64: return "f9";
+ case gcc_dwarf_f10_mips64: return "f10";
+ case gcc_dwarf_f11_mips64: return "f11";
+ case gcc_dwarf_f12_mips64: return "f12";
+ case gcc_dwarf_f13_mips64: return "f13";
+ case gcc_dwarf_f14_mips64: return "f14";
+ case gcc_dwarf_f15_mips64: return "f15";
+ case gcc_dwarf_f16_mips64: return "f16";
+ case gcc_dwarf_f17_mips64: return "f17";
+ case gcc_dwarf_f18_mips64: return "f18";
+ case gcc_dwarf_f19_mips64: return "f19";
+ case gcc_dwarf_f20_mips64: return "f20";
+ case gcc_dwarf_f21_mips64: return "f21";
+ case gcc_dwarf_f22_mips64: return "f22";
+ case gcc_dwarf_f23_mips64: return "f23";
+ case gcc_dwarf_f24_mips64: return "f24";
+ case gcc_dwarf_f25_mips64: return "f25";
+ case gcc_dwarf_f26_mips64: return "f26";
+ case gcc_dwarf_f27_mips64: return "f27";
+ case gcc_dwarf_f28_mips64: return "f28";
+ case gcc_dwarf_f29_mips64: return "f29";
+ case gcc_dwarf_f30_mips64: return "f30";
+ case gcc_dwarf_f31_mips64: return "f31";
case gcc_dwarf_fcsr_mips64: return "fcsr";
case gcc_dwarf_fir_mips64: return "fir";
}
@@ -397,6 +410,9 @@ EmulateInstructionMIPS64::GetOpcodeForIn
{ "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" },
{ "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" },
+ { "SW", &EmulateInstructionMIPS64::Emulate_SW, "SW rt,offset(rs)" },
+ { "LW", &EmulateInstructionMIPS64::Emulate_LW, "LW rt,offset(rs)" },
+
//----------------------------------------------------------------------
// Branch instructions
//----------------------------------------------------------------------
@@ -644,35 +660,95 @@ EmulateInstructionMIPS64::Emulate_DADDiu
}
bool
+EmulateInstructionMIPS64::Emulate_SW (llvm::MCInst& insn)
+{
+ bool success = false;
+ uint32_t base;
+ int64_t imm, address;
+ Context bad_vaddr_context;
+
+ base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
+ imm = insn.getOperand(2).getImm();
+
+ RegisterInfo reg_info_base;
+ if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base))
+ return false;
+
+ /* read base register */
+ address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success);
+ if (!success)
+ return false;
+
+ /* destination address */
+ address = address + imm;
+
+ /* Set the bad_vaddr register with base address used in the instruction */
+ bad_vaddr_context.type = eContextInvalid;
+ WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address);
+
+ return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_LW (llvm::MCInst& insn)
+{
+ bool success = false;
+ uint32_t base;
+ int64_t imm, address;
+ Context bad_vaddr_context;
+
+ base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
+ imm = insn.getOperand(2).getImm();
+
+ RegisterInfo reg_info_base;
+ if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base))
+ return false;
+
+ /* read base register */
+ address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success);
+ if (!success)
+ return false;
+
+ /* destination address */
+ address = address + imm;
+
+ /* Set the bad_vaddr register with base address used in the instruction */
+ bad_vaddr_context.type = eContextInvalid;
+ WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address);
+
+ return true;
+}
+
+bool
EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn)
{
+ uint64_t address;
+ RegisterInfo reg_info_base;
+ RegisterInfo reg_info_src;
bool success = false;
uint32_t imm16 = insn.getOperand(2).getImm();
uint64_t imm = SignedBits(imm16, 15, 0);
uint32_t src, base;
+ Context bad_vaddr_context;
src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
- /* We look for sp based non-volatile register stores */
- if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src))
- {
- uint64_t address;
- RegisterInfo reg_info_base;
- RegisterInfo reg_info_src;
-
- if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)
- || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src))
- return false;
+ if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)
+ || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src))
+ return false;
- /* read SP */
- address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success);
- if (!success)
- return false;
+ /* read SP */
+ address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success);
+ if (!success)
+ return false;
- /* destination address */
- address = address + imm;
+ /* destination address */
+ address = address + imm;
+ /* We look for sp based non-volatile register stores */
+ if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src))
+ {
Context context;
RegisterValue data_src;
context.type = eContextPushRegisterOnStack;
@@ -689,11 +765,13 @@ EmulateInstructionMIPS64::Emulate_SD (ll
if (!WriteMemory (context, address, buffer, reg_info_src.byte_size))
return false;
-
- return true;
}
- return false;
+ /* Set the bad_vaddr register with base address used in the instruction */
+ bad_vaddr_context.type = eContextInvalid;
+ WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address);
+
+ return true;
}
bool
Modified: vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
==============================================================================
--- vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -128,6 +128,12 @@ protected:
Emulate_SD (llvm::MCInst& insn);
bool
+ Emulate_SW (llvm::MCInst& insn);
+
+ bool
+ Emulate_LW (llvm::MCInst& insn);
+
+ bool
Emulate_LD (llvm::MCInst& insn);
bool
Modified: vendor/lldb/dist/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -1437,6 +1437,25 @@ ObjectFileELF::GetSectionHeaderInfo(Sect
assert(spec_ostype == ostype);
}
+ if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel
+ || arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el)
+ {
+ switch (header.e_flags & llvm::ELF::EF_MIPS_ARCH_ASE)
+ {
+ case llvm::ELF::EF_MIPS_MICROMIPS:
+ arch_spec.SetFlags (ArchSpec::eMIPSAse_micromips);
+ break;
+ case llvm::ELF::EF_MIPS_ARCH_ASE_M16:
+ arch_spec.SetFlags (ArchSpec::eMIPSAse_mips16);
+ break;
+ case llvm::ELF::EF_MIPS_ARCH_ASE_MDMX:
+ arch_spec.SetFlags (ArchSpec::eMIPSAse_mdmx);
+ break;
+ default:
+ break;
+ }
+ }
+
// If there are no section headers we are done.
if (header.e_shnum == 0)
return 0;
@@ -1483,6 +1502,22 @@ ObjectFileELF::GetSectionHeaderInfo(Sect
I->section_name = name;
+ if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel
+ || arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el)
+ {
+ if (header.sh_type == SHT_MIPS_ABIFLAGS)
+ {
+ DataExtractor data;
+ if (section_size && (data.SetData (object_data, header.sh_offset, section_size) == section_size))
+ {
+ lldb::offset_t ase_offset = 12; // MIPS ABI Flags Version: 0
+ uint32_t arch_flags = arch_spec.GetFlags ();
+ arch_flags |= data.GetU32 (&ase_offset);
+ arch_spec.SetFlags (arch_flags);
+ }
+ }
+ }
+
if (name == g_sect_name_gnu_debuglink)
{
DataExtractor data;
Modified: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -57,7 +57,7 @@ typedef struct _GPR
uint64_t pc;
uint64_t ic;
uint64_t dummy;
-} GPR;
+} GPR_freebsd_mips;
//---------------------------------------------------------------------------
// Include RegisterInfos_mips64 to declare our g_register_infos_mips64 structure.
@@ -74,7 +74,7 @@ RegisterContextFreeBSD_mips64::RegisterC
size_t
RegisterContextFreeBSD_mips64::GetGPRSize() const
{
- return sizeof(GPR);
+ return sizeof(GPR_freebsd_mips);
}
const RegisterInfo *
Modified: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -14,55 +14,14 @@
#include "RegisterContextLinux_mips.h"
// Internal codes for mips registers
-#include "lldb-mips64-register-enums.h"
-#include "RegisterContext_mips64.h"
+#include "lldb-mips-linux-register-enums.h"
+
+// For GP and FP buffers
+#include "RegisterContext_mips.h"
using namespace lldb_private;
using namespace lldb;
-// GP registers
-typedef struct _GPR
-{
- uint32_t zero;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r4;
- uint32_t r5;
- uint32_t r6;
- uint32_t r7;
- uint32_t r8;
- uint32_t r9;
- uint32_t r10;
- uint32_t r11;
- uint32_t r12;
- uint32_t r13;
- uint32_t r14;
- uint32_t r15;
- uint32_t r16;
- uint32_t r17;
- uint32_t r18;
- uint32_t r19;
- uint32_t r20;
- uint32_t r21;
- uint32_t r22;
- uint32_t r23;
- uint32_t r24;
- uint32_t r25;
- uint32_t r26;
- uint32_t r27;
- uint32_t gp;
- uint32_t sp;
- uint32_t r30;
- uint32_t ra;
- uint32_t mullo;
- uint32_t mulhi;
- uint32_t pc;
- uint32_t badvaddr;
- uint32_t sr;
- uint32_t cause;
-} GPR;
-
//---------------------------------------------------------------------------
// Include RegisterInfos_mips to declare our g_register_infos_mips structure.
//---------------------------------------------------------------------------
@@ -78,7 +37,7 @@ RegisterContextLinux_mips::RegisterConte
size_t
RegisterContextLinux_mips::GetGPRSize() const
{
- return sizeof(GPR);
+ return sizeof(GPR_linux_mips);
}
const RegisterInfo *
@@ -100,3 +59,9 @@ RegisterContextLinux_mips::GetRegisterCo
{
return static_cast<uint32_t> (sizeof (g_register_infos_mips) / sizeof (g_register_infos_mips [0]));
}
+
+uint32_t
+RegisterContextLinux_mips::GetUserRegisterCount () const
+{
+ return static_cast<uint32_t> (k_num_user_registers_mips);
+}
Modified: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.h
==============================================================================
--- vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -27,6 +27,9 @@ public:
uint32_t
GetRegisterCount () const override;
+
+ uint32_t
+ GetUserRegisterCount () const override;
};
#endif
Modified: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp
==============================================================================
--- vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp Sun Sep 6 18:37:19 2015 (r287514)
@@ -15,63 +15,22 @@
// For GDB, GCC and DWARF Register numbers
#include "RegisterContextLinux_mips64.h"
-// Internal codes for all mips64 registers
-#include "lldb-mips64-register-enums.h"
-#include "RegisterContext_mips64.h"
+// For GP and FP buffers
+#include "RegisterContext_mips.h"
+
+// Internal codes for all mips32 and mips64 registers
+#include "lldb-mips-linux-register-enums.h"
using namespace lldb;
using namespace lldb_private;
-// GP registers
-typedef struct _GPR
-{
- uint64_t zero;
- uint64_t r1;
- uint64_t r2;
- uint64_t r3;
- uint64_t r4;
- uint64_t r5;
- uint64_t r6;
- uint64_t r7;
- uint64_t r8;
- uint64_t r9;
- uint64_t r10;
- uint64_t r11;
- uint64_t r12;
- uint64_t r13;
- uint64_t r14;
- uint64_t r15;
- uint64_t r16;
- uint64_t r17;
- uint64_t r18;
- uint64_t r19;
- uint64_t r20;
- uint64_t r21;
- uint64_t r22;
- uint64_t r23;
- uint64_t r24;
- uint64_t r25;
- uint64_t r26;
- uint64_t r27;
- uint64_t gp;
- uint64_t sp;
- uint64_t r30;
- uint64_t ra;
- uint64_t mullo;
- uint64_t mulhi;
- uint64_t pc;
- uint64_t badvaddr;
- uint64_t sr;
- uint64_t cause;
- uint64_t ic;
- uint64_t dummy;
-} GPR;
-
//---------------------------------------------------------------------------
// Include RegisterInfos_mips64 to declare our g_register_infos_mips64 structure.
//---------------------------------------------------------------------------
#define DECLARE_REGISTER_INFOS_MIPS64_STRUCT
+#define LINUX_MIPS64
#include "RegisterInfos_mips64.h"
+#undef LINUX_MIPS64
#undef DECLARE_REGISTER_INFOS_MIPS64_STRUCT
//---------------------------------------------------------------------------
@@ -115,17 +74,35 @@ GetRegisterInfoCount (const ArchSpec &ta
}
}
+uint32_t
+GetUserRegisterInfoCount (const ArchSpec &target_arch)
+{
+ switch (target_arch.GetMachine())
+ {
+ case llvm::Triple::mips:
+ case llvm::Triple::mipsel:
+ return static_cast<uint32_t> (k_num_user_registers_mips);
+ case llvm::Triple::mips64el:
+ case llvm::Triple::mips64:
+ return static_cast<uint32_t> (k_num_user_registers_mips64);
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
RegisterContextLinux_mips64::RegisterContextLinux_mips64(const ArchSpec &target_arch) :
lldb_private::RegisterInfoInterface(target_arch),
m_register_info_p (GetRegisterInfoPtr (target_arch)),
- m_register_info_count (GetRegisterInfoCount (target_arch))
+ m_register_info_count (GetRegisterInfoCount (target_arch)),
+ m_user_register_count (GetUserRegisterInfoCount (target_arch))
{
}
size_t
RegisterContextLinux_mips64::GetGPRSize() const
{
- return sizeof(GPR);
+ return sizeof(GPR_linux_mips);
}
const RegisterInfo *
@@ -140,4 +117,10 @@ RegisterContextLinux_mips64::GetRegister
return m_register_info_count;
}
+uint32_t
+RegisterContextLinux_mips64::GetUserRegisterCount () const
+{
+ return m_user_register_count;
+}
+
#endif
Modified: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h
==============================================================================
--- vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -30,9 +30,13 @@ public:
uint32_t
GetRegisterCount () const override;
+ uint32_t
+ GetUserRegisterCount () const override;
+
private:
const lldb_private::RegisterInfo *m_register_info_p;
uint32_t m_register_info_count;
+ uint32_t m_user_register_count;
};
#endif
Modified: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h
==============================================================================
--- vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h Sun Sep 6 18:37:02 2015 (r287513)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -12,8 +12,8 @@
#include "lldb/Core/Log.h"
#include "RegisterContextPOSIX.h"
-#include "RegisterContext_mips64.h"
-#include "lldb-mips64-register-enums.h"
+#include "RegisterContext_mips.h"
+#include "lldb-mips-freebsd-register-enums.h"
using namespace lldb_private;
Added: vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContext_mips.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor/lldb/dist/source/Plugins/Process/Utility/RegisterContext_mips.h Sun Sep 6 18:37:19 2015 (r287514)
@@ -0,0 +1,611 @@
+//===-- RegisterContext_mips.h --------------------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef liblldb_RegisterContext_mips64_H_
+#define liblldb_RegisterContext_mips64_H_
+
+// eh_frame and DWARF Register numbers (eRegisterKindEHFrame & eRegisterKindDWARF)
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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