svn commit: r237667 - in user/jceel/soc2012_armv6/sys: arm/arm
arm/conf arm/include arm/mv arm/mv/discovery boot/fdt/dts dev/mge
Jakub Wojciech Klama
jceel at FreeBSD.org
Wed Jun 27 21:47:28 UTC 2012
Author: jceel
Date: Wed Jun 27 21:47:27 2012
New Revision: 237667
URL: http://svn.freebsd.org/changeset/base/237667
Log:
Replace arm/mv port with one got from HEAD, as on armv6 branch
Marvell targets other than armadaxp (for example DB-88F5XXX, 6XXX,
Sheevaplug, etc) are defunct.
Modified:
user/jceel/soc2012_armv6/sys/arm/arm/cpufunc.c
user/jceel/soc2012_armv6/sys/arm/conf/DB-88F6XXX
user/jceel/soc2012_armv6/sys/arm/include/fdt.h
user/jceel/soc2012_armv6/sys/arm/mv/common.c
user/jceel/soc2012_armv6/sys/arm/mv/discovery/discovery.c
user/jceel/soc2012_armv6/sys/arm/mv/files.mv
user/jceel/soc2012_armv6/sys/arm/mv/mv_machdep.c
user/jceel/soc2012_armv6/sys/arm/mv/mvreg.h
user/jceel/soc2012_armv6/sys/arm/mv/mvvar.h
user/jceel/soc2012_armv6/sys/arm/mv/mvwin.h
user/jceel/soc2012_armv6/sys/arm/mv/std.mv
user/jceel/soc2012_armv6/sys/arm/mv/timer.c
user/jceel/soc2012_armv6/sys/boot/fdt/dts/db88f6281.dts
user/jceel/soc2012_armv6/sys/dev/mge/if_mge.c
user/jceel/soc2012_armv6/sys/dev/mge/if_mgevar.h
Modified: user/jceel/soc2012_armv6/sys/arm/arm/cpufunc.c
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/arm/cpufunc.c Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/arm/cpufunc.c Wed Jun 27 21:47:27 2012 (r237667)
@@ -1297,7 +1297,7 @@ set_cpufuncs()
get_cachetype_cp15();
pmap_pte_init_generic();
goto out;
- } else if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM926ES ||
+ } else if (cputype == CPU_ID_ARM926EJS || /*cputype == CPU_ID_ARM926ES ||*/
cputype == CPU_ID_ARM1026EJS) {
cpufuncs = armv5_ec_cpufuncs;
get_cachetype_cp15();
Modified: user/jceel/soc2012_armv6/sys/arm/conf/DB-88F6XXX
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/conf/DB-88F6XXX Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/conf/DB-88F6XXX Wed Jun 27 21:47:27 2012 (r237667)
@@ -44,8 +44,8 @@ options DIAGNOSTIC
#options INVARIANTS #Enable calls of extra sanity checking
#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
options KDB
-options WITNESS #Enable checks to detect deadlocks and cycles
-options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
#options WITNESS_KDB
device pci
@@ -65,26 +65,31 @@ device mii
device e1000phy
device bpf
-device cesa # Marvell security engine
-device crypto
-device cryptodev
+#device cesa # Marvell security engine
+#device crypto
+#device cryptodev
# USB
-options USB_DEBUG # enable debug msgs
-device usb
-device ehci
-device umass
-device scbus
-device pass
-device da
+#options USB_DEBUG # enable debug msgs
+#device usb
+#device ehci
+#device umass
+#device scbus
+#device pass
+#device da
# I2C (TWSI)
-device iic
-device iicbus
+#device iic
+#device iicbus
# SATA
-device mvs
+#device mvs
+
+# Flash
+device cfi
+device cfid
# Flattened Device Tree
options FDT
+options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=db88f6281.dts
Modified: user/jceel/soc2012_armv6/sys/arm/include/fdt.h
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/include/fdt.h Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/include/fdt.h Wed Jun 27 21:47:27 2012 (r237667)
@@ -71,7 +71,9 @@ struct mem_region {
vm_size_t mr_size;
};
+int fdt_localbus_devmap(phandle_t, struct pmap_devmap *, int, int *);
int fdt_pci_devmap(phandle_t, struct pmap_devmap *devmap, vm_offset_t,
vm_offset_t);
#endif /* _MACHINE_FDT_H_ */
+
Modified: user/jceel/soc2012_armv6/sys/arm/mv/common.c
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/mv/common.c Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/mv/common.c Wed Jun 27 21:47:27 2012 (r237667)
@@ -1,5 +1,5 @@
/*-
- * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
+ * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
* All rights reserved.
*
* Developed by Semihalf.
@@ -29,8 +29,6 @@
* SUCH DAMAGE.
*/
-#include "opt_global.h"
-
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
@@ -38,27 +36,17 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
-#include <sys/malloc.h>
-#include <sys/kdb.h>
-#include <sys/reboot.h>
#include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h>
#include <machine/bus.h>
#include <machine/fdt.h>
-#include <machine/vmparam.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
#include <arm/mv/mvwin.h>
-
-MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
-
-#define IDMA_DEBUG
-#undef IDMA_DEBUG
-
#define MAX_CPU_WIN 5
#ifdef DEBUG
@@ -76,9 +64,7 @@ MALLOC_DEFINE(M_IDMA, "idma", "idma dma
static int win_eth_can_remap(int i);
-#ifndef SOC_MV_FREY
static int decode_win_cpu_valid(void);
-#endif
static int decode_win_usb_valid(void);
static int decode_win_eth_valid(void);
static int decode_win_pcie_valid(void);
@@ -87,11 +73,10 @@ static int decode_win_cesa_valid(void);
static int decode_win_idma_valid(void);
static int decode_win_xor_valid(void);
-#ifndef SOC_MV_FREY
static void decode_win_cpu_setup(void);
-#endif
static void decode_win_usb_setup(u_long);
static void decode_win_eth_setup(u_long);
+static void decode_win_pcie_setup(u_long);
static void decode_win_sata_setup(u_long);
static void decode_win_cesa_setup(u_long);
static void decode_win_idma_setup(u_long);
@@ -108,6 +93,7 @@ static int fdt_get_ranges(const char *,
static int win_cpu_from_dt(void);
static int fdt_win_setup(void);
+static uint32_t used_cpu_wins;
static uint32_t dev_mask = 0;
static int cpu_wins_no = 0;
static int eth_port = 0;
@@ -115,7 +101,7 @@ static int usb_port = 0;
static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
-const struct decode_win *cpu_wins = cpu_win_tbl;
+static const struct decode_win *cpu_wins = cpu_win_tbl;
typedef void (*decode_win_setup_t)(u_long);
typedef void (*dump_win_t)(u_long);
@@ -265,22 +251,13 @@ cpu_extra_feat(void)
uint32_t ef = 0;
soc_id(&dev, &rev);
-
- switch (dev) {
- case MV_DEV_88F6281:
- case MV_DEV_88RC8180:
- case MV_DEV_MV78100_Z0:
- case MV_DEV_MV78100:
+ if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100_Z0 ||
+ dev == MV_DEV_MV78100)
__asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
- break;
- case MV_DEV_88F5182:
- case MV_DEV_88F5281:
+ else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
__asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
- break;
- default:
- if (bootverbose)
- printf("This ARM Core does not support any extra features\n");
- }
+ else if (bootverbose)
+ printf("This ARM Core does not support any extra features\n");
return (ef);
}
@@ -293,7 +270,7 @@ uint32_t
soc_power_ctrl_get(uint32_t mask)
{
-#if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY)
+#ifndef SOC_MV_ORION
if (mask != CPU_PM_CTRL_NONE)
mask &= read_cpu_ctrl(CPU_PM_CTRL);
@@ -311,7 +288,7 @@ void
soc_power_ctrl_set(uint32_t mask)
{
-#if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS)
+#ifndef SOC_MV_ORION
if (mask != CPU_PM_CTRL_NONE)
write_cpu_ctrl(CPU_PM_CTRL, mask);
#endif
@@ -334,7 +311,7 @@ soc_id(uint32_t *dev, uint32_t *rev)
static void
soc_identify(void)
{
- uint32_t d, r, size, mode;
+ uint32_t d, r;
const char *dev;
const char *rev;
@@ -374,35 +351,12 @@ soc_identify(void)
else if (r == 3)
rev = "A1";
break;
- case MV_DEV_88RC8180:
- dev = "Marvell 88RC8180";
- break;
- case MV_DEV_88RC9480:
- dev = "Marvell 88RC9480";
- break;
- case MV_DEV_88RC9580:
- dev = "Marvell 88RC9580";
- break;
- case MV_DEV_88F6781:
- dev = "Marvell 88F6781";
- if (r == 2)
- rev = "Y0";
- break;
case MV_DEV_MV78100_Z0:
dev = "Marvell MV78100 Z0";
break;
case MV_DEV_MV78100:
dev = "Marvell MV78100";
break;
- case MV_DEV_MV78160:
- dev = "Marvell MV78160";
- break;
- case MV_DEV_MV78260:
- dev = "Marvell MV78260";
- break;
- case MV_DEV_MV78460:
- dev = "Marvell MV78460";
- break;
default:
dev = "UNKNOWN";
break;
@@ -413,28 +367,7 @@ soc_identify(void)
printf(" rev %s", rev);
printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
- mode = read_cpu_ctrl(CPU_CONFIG);
- printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
- (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
- (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
-
- switch (d) {
- case MV_DEV_88F6281:
- mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
- printf(" 256KB 4-way set-associative %s unified L2 cache\n",
- mode ? "write-through" : "write-back");
- break;
- case MV_DEV_MV78100:
- mode = read_cpu_ctrl(CPU_CONTROL);
- size = mode & CPU_CONTROL_L2_SIZE;
- mode = mode & CPU_CONTROL_L2_MODE;
- printf(" %s set-associative %s unified L2 cache\n",
- size ? "256KB 4-way" : "512KB 8-way",
- mode ? "write-through" : "write-back");
- break;
- default:
- break;
- }
+ /* TODO add info on currently set endianess */
}
static void
@@ -451,17 +384,6 @@ platform_identify(void *dummy)
SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify,
NULL);
-#ifdef KDB
-static void
-mv_enter_debugger(void *dummy)
-{
-
- if (boothowto & RB_KDB)
- kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
-}
-SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL);
-#endif
-
int
soc_decode_win(void)
{
@@ -481,7 +403,6 @@ soc_decode_win(void)
/* Retrieve our ID: some windows facilities vary between SoC models */
soc_id(&dev, &rev);
-#ifndef SOC_MV_FREY
if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
!decode_win_eth_valid() || !decode_win_idma_valid() ||
!decode_win_pcie_valid() || !decode_win_sata_valid() ||
@@ -489,13 +410,6 @@ soc_decode_win(void)
return (EINVAL);
decode_win_cpu_setup();
-#else
- if (!decode_win_usb_valid() ||
- !decode_win_eth_valid() || !decode_win_idma_valid() ||
- !decode_win_pcie_valid() || !decode_win_sata_valid() ||
- !decode_win_cesa_valid() || !decode_win_xor_valid())
- return (EINVAL);
-#endif
if (MV_DUMP_WIN)
soc_dump_decode_win();
@@ -510,7 +424,6 @@ soc_decode_win(void)
/**************************************************************************
* Decode windows registers accessors
**************************************************************************/
-#if !defined(SOC_MV_FREY)
WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
@@ -519,7 +432,9 @@ WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_C
WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
-#endif
+
+WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
+WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
@@ -558,10 +473,7 @@ WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_
WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
-WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
-WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
-WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
-WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
+WIN_REG_BASE_IDX_WR(pcie, bar, MV_PCIE_BAR);
WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE)
WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE)
@@ -578,44 +490,7 @@ WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN
WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
-#ifndef SOC_MV_DOVE
-WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
-WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
-#else
-/*
- * On 88F6781 (Dove) SoC DDR Controller is accessed through
- * single MBUS <-> AXI bridge. In this case we provide emulated
- * ddr_br_read() and ddr_sz_read() functions to keep compatibility
- * with common decoding windows setup code.
- */
-
-static inline uint32_t ddr_br_read(int i)
-{
- uint32_t mmap;
-
- /* Read Memory Address Map Register for CS i */
- mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
-
- /* Return CS i base address */
- return (mmap & 0xFF000000);
-}
-
-static inline uint32_t ddr_sz_read(int i)
-{
- uint32_t mmap, size;
-
- /* Read Memory Address Map Register for CS i */
- mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
- /* Extract size of CS space in 64kB units */
- size = (1 << ((mmap >> 16) & 0x0F));
-
- /* Return CS size and enable/disable status */
- return (((size - 1) << 16) | (mmap & 0x01));
-}
-#endif
-
-#if !defined(SOC_MV_FREY)
/**************************************************************************
* Decode windows helper routines
**************************************************************************/
@@ -661,10 +536,8 @@ win_cpu_can_remap(int i)
if ((dev == MV_DEV_88F5182 && i < 2) ||
(dev == MV_DEV_88F5281 && i < 4) ||
(dev == MV_DEV_88F6281 && i < 4) ||
- (dev == MV_DEV_88RC8180 && i < 2) ||
- (dev == MV_DEV_88F6781 && i < 4) ||
- (dev == MV_DEV_MV78100_Z0 && i < 8) ||
- ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
+ (dev == MV_DEV_MV78100 && i < 8) ||
+ (dev == MV_DEV_MV78100_Z0 && i < 8))
return (1);
return (0);
@@ -717,7 +590,7 @@ decode_win_cpu_valid(void)
rv = 0;
}
- if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) {
+ if (cpu_wins[i].remap >= 0 && win_cpu_can_remap(i) != 1) {
printf("CPU window#%d: not capable of remapping, but "
"val 0x%08x defined\n", i, cpu_wins[i].remap);
rv = 0;
@@ -737,13 +610,6 @@ decode_win_cpu_valid(void)
continue;
}
- if (b != (b & ~(s - 1))) {
- printf("CPU window#%d: address 0x%08x is not aligned "
- "to 0x%08x\n", i, b, s);
- rv = 0;
- continue;
- }
-
j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
if (j >= 0) {
printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
@@ -759,39 +625,21 @@ decode_win_cpu_valid(void)
int
decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
- vm_paddr_t remap)
+ int remap)
{
uint32_t br, cr;
- int win, i;
+ int win;
- if (remap == ~0) {
- win = MV_WIN_CPU_MAX - 1;
- i = -1;
- } else {
- win = 0;
- i = 1;
- }
+ if (used_cpu_wins >= MV_WIN_CPU_MAX)
+ return (0);
- while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {
- cr = win_cpu_cr_read(win);
- if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
- break;
- if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) |
- (0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
- ((attr << MV_WIN_CPU_ATTR_SHIFT) |
- (target << MV_WIN_CPU_TARGET_SHIFT)))
- break;
- win += i;
- }
- if ((win < 0) || (win >= MV_WIN_CPU_MAX) ||
- ((remap != ~0) && (win_cpu_can_remap(win) == 0)))
- return (-1);
+ win = used_cpu_wins++;
br = base & 0xffff0000;
win_cpu_br_write(win, br);
if (win_cpu_can_remap(win)) {
- if (remap != ~0) {
+ if (remap >= 0) {
win_cpu_remap_l_write(win, remap & 0xffff0000);
win_cpu_remap_h_write(win, 0);
} else {
@@ -805,8 +653,7 @@ decode_win_cpu_set(int target, int attr,
}
}
- cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |
- (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT;
+ cr = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
win_cpu_cr_write(win, cr);
return (0);
@@ -817,6 +664,8 @@ decode_win_cpu_setup(void)
{
int i;
+ used_cpu_wins = 0;
+
/* Disable all CPU windows */
for (i = 0; i < MV_WIN_CPU_MAX; i++) {
win_cpu_cr_write(i, 0);
@@ -834,7 +683,7 @@ decode_win_cpu_setup(void)
cpu_wins[i].size, cpu_wins[i].remap);
}
-#endif
+
/*
* Check if we're able to cover all active DDR banks.
*/
@@ -887,13 +736,6 @@ ddr_size(int i)
uint32_t
ddr_attr(int i)
{
- uint32_t dev, rev;
-
- soc_id(&dev, &rev);
- if (dev == MV_DEV_88RC8180)
- return ((ddr_sz_read(i) & 0xf0) >> 4);
- if (dev == MV_DEV_88F6781)
- return (0);
return (i == 0 ? 0xe :
(i == 1 ? 0xd :
@@ -904,21 +746,8 @@ ddr_attr(int i)
uint32_t
ddr_target(int i)
{
- uint32_t dev, rev;
- soc_id(&dev, &rev);
- if (dev == MV_DEV_88RC8180) {
- i = (ddr_sz_read(i) & 0xf0) >> 4;
- return (i == 0xe ? 0xc :
- (i == 0xd ? 0xd :
- (i == 0xb ? 0xe :
- (i == 0x7 ? 0xf : 0xc))));
- }
-
- /*
- * On SOCs other than 88RC8180 Mbus unit ID for
- * DDR SDRAM controller is always 0x0.
- */
+ /* Mbus unit ID is 0x0 for DDR SDRAM controller */
return (0);
}
@@ -1001,7 +830,7 @@ win_eth_can_remap(int i)
/* ETH encode windows 0-3 have remap capability */
if (i < 4)
return (1);
-
+
return (0);
}
@@ -1062,12 +891,6 @@ decode_win_eth_dump(u_long base)
win_eth_epap_read(base));
}
-#if defined(SOC_MV_LOKIPLUS)
-#define MV_WIN_ETH_DDR_TRGT(n) 0
-#else
-#define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n)
-#endif
-
static void
decode_win_eth_setup(u_long base)
{
@@ -1094,7 +917,7 @@ decode_win_eth_setup(u_long base)
for (i = 0; i < MV_WIN_DDR_MAX; i++)
if (ddr_is_active(i)) {
- br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
+ br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
sz = ((ddr_size(i) - 1) & 0xffff0000);
/* Set the first free ETH window */
@@ -1128,21 +951,15 @@ decode_win_eth_valid(void)
* PCIE windows routines
**************************************************************************/
-void
+static void
decode_win_pcie_setup(u_long base)
{
- uint32_t size = 0, ddrbase = ~0;
+ uint32_t size = 0;
uint32_t cr, br;
int i, j;
- for (i = 0; i < MV_PCIE_BAR_MAX; i++) {
- pcie_bar_br_write(base, i,
- MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
- if (i < 3)
- pcie_bar_brh_write(base, i, 0);
- if (i > 0)
- pcie_bar_cr_write(base, i, 0);
- }
+ for (i = 0; i < MV_PCIE_BAR_MAX; i++)
+ pcie_bar_write(base, i, 0);
for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
win_pcie_cr_write(base, i, 0);
@@ -1150,13 +967,6 @@ decode_win_pcie_setup(u_long base)
win_pcie_remap_write(base, i, 0);
}
- /* On End-Point only set BAR size to 1MB regardless of DDR size */
- if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL)
- & MV_PCIE_ROOT_CMPLX) == 0) {
- pcie_bar_cr_write(base, 1, 0xf0000 | 1);
- return;
- }
-
for (i = 0; i < MV_WIN_DDR_MAX; i++) {
if (ddr_is_active(i)) {
/* Map DDR to BAR 1 */
@@ -1164,8 +974,6 @@ decode_win_pcie_setup(u_long base)
size += ddr_size(i) & 0xffff0000;
cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
br = ddr_base(i);
- if (br < ddrbase)
- ddrbase = br;
/* Use the first available PCIE window */
for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
@@ -1185,11 +993,7 @@ decode_win_pcie_setup(u_long base)
* form value passed to register to get correct value.
*/
size -= 0x10000;
- pcie_bar_cr_write(base, 1, size | 1);
- pcie_bar_br_write(base, 1, ddrbase |
- MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
- pcie_bar_br_write(base, 0, fdt_immr_pa |
- MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
+ pcie_bar_write(base, 0, size | 1);
}
static int
@@ -1475,6 +1279,7 @@ xor_ctrl_write(u_long base, int i, int c
/*
* Set channel protection 'val' for window 'w' on channel 'c'
*/
+
static void
xor_chan_write(u_long base, int c, int e, int w, int val)
{
@@ -1932,7 +1737,7 @@ win_cpu_from_dt(void)
/* Retrieve 'ranges' property of '/localbus' node. */
if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
&tuples, &tuple_size)) != 0)
- return (0);
+ return (err);
/*
* Fill CPU decode windows table.
@@ -1947,9 +1752,9 @@ win_cpu_from_dt(void)
cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
- cpu_win_tbl[t].remap = ~0;
+ cpu_win_tbl[t].remap = -1;
debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
- "size = 0x%0x remap = 0x%0x\n", cpu_win_tbl[t].target,
+ "size = 0x%0x remap = %d\n", cpu_win_tbl[t].target,
cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
}
@@ -1976,7 +1781,7 @@ moveon:
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR;
cpu_win_tbl[t].base = sram_base;
cpu_win_tbl[t].size = sram_size;
- cpu_win_tbl[t].remap = ~0;
+ cpu_win_tbl[t].remap = -1;
debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
return (0);
@@ -1994,12 +1799,15 @@ fdt_win_setup(void)
if (node == -1)
panic("fdt_win_setup: no root node");
+ node = fdt_find_compatible(node, "simple-bus", 1);
+ if (node == 0)
+ return (ENXIO);
+
/*
- * Traverse through all children of root and simple-bus nodes.
- * For each found device retrieve decode windows data (if applicable).
+ * Traverse through all children of simple-bus node, and retrieve
+ * decode windows data for devices (if applicable).
*/
- child = OF_child(node);
- while (child != 0) {
+ for (child = OF_child(node); child != 0; child = OF_peer(child))
for (i = 0; soc_nodes[i].compat != NULL; i++) {
soc_node = &soc_nodes[i];
@@ -2011,7 +1819,7 @@ fdt_win_setup(void)
if (err != 0)
return (err);
- base = (base & 0x000fffff) | fdt_immr_va;
+ base += fdt_immr_va;
if (soc_node->decode_handler != NULL)
soc_node->decode_handler(base);
else
@@ -2021,19 +1829,6 @@ fdt_win_setup(void)
soc_node->dump_handler(base);
}
- /*
- * Once done with root-level children let's move down to
- * simple-bus and its children.
- */
- child = OF_peer(child);
- if ((child == 0) && (node == OF_finddevice("/"))) {
- node = fdt_find_compatible(node, "simple-bus", 1);
- if (node == 0)
- return (ENXIO);
- child = OF_child(node);
- }
- }
-
return (0);
}
@@ -2064,8 +1859,7 @@ fdt_pic_decode_ic(phandle_t node, pcell_
int *pol)
{
- if (!fdt_is_compatible(node, "mrvl,pic") &&
- !fdt_is_compatible(node, "mrvl,mpic"))
+ if (!fdt_is_compatible(node, "mrvl,pic"))
return (ENXIO);
*interrupt = fdt32_to_cpu(intr[0]);
Modified: user/jceel/soc2012_armv6/sys/arm/mv/discovery/discovery.c
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/mv/discovery/discovery.c Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/mv/discovery/discovery.c Wed Jun 27 21:47:27 2012 (r237667)
@@ -43,6 +43,30 @@ __FBSDID("$FreeBSD$");
#include <arm/mv/mvvar.h>
#include <arm/mv/mvwin.h>
+/*
+ * Virtual address space layout:
+ * -----------------------------
+ * 0x0000_0000 - 0xBFFF_FFFF : User Process (3 GB)
+ * 0xC000_0000 - virtual_avail : Kernel Reserved (text, data, page tables,
+ * : stack etc.)
+ * virtual-avail - 0xEFFF_FFFF : KVA (virtual_avail is typically < 0xc0a0_0000)
+ * 0xF000_0000 - 0xF0FF_FFFF : No-Cache allocation area (16 MB)
+ * 0xF100_0000 - 0xF10F_FFFF : SoC Integrated devices registers range (1 MB)
+ * 0xF110_0000 - 0xF11F_FFFF : PCI-Express I/O space (1MB)
+ * 0xF120_0000 - 0xF12F_FFFF : PCI I/O space (1MB)
+ * 0xF130_0000 - 0xF52F_FFFF : PCI-Express memory space (64MB)
+ * 0xF530_0000 - 0xF92F_FFFF : PCI memory space (64MB)
+ * 0xF930_0000 - 0xF93F_FFFF : Device Bus: BOOT (1 MB)
+ * 0xF940_0000 - 0xF94F_FFFF : Device Bus: CS0 (1 MB)
+ * 0xF950_0000 - 0xFB4F_FFFF : Device Bus: CS1 (32 MB)
+ * 0xFB50_0000 - 0xFB5F_FFFF : Device Bus: CS2 (1 MB)
+ * 0xFB60_0000 - 0xFFFE_FFFF : Unused (~74MB)
+ * 0xFFFF_0000 - 0xFFFF_0FFF : 'High' vectors page (4 kB)
+ * 0xFFFF_1000 - 0xFFFF_1FFF : ARM_TP_ADDRESS/RAS page (4 kB)
+ * 0xFFFF_2000 - 0xFFFF_FFFF : Unused (56 kB)
+ */
+
+
struct resource_spec mv_gpio_res[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
Modified: user/jceel/soc2012_armv6/sys/arm/mv/files.mv
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/mv/files.mv Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/mv/files.mv Wed Jun 27 21:47:27 2012 (r237667)
@@ -14,18 +14,16 @@
#
arm/arm/bus_space_generic.c standard
arm/arm/cpufunc_asm_arm10.S standard
-arm/arm/cpufunc_asm_arm11.S standard
-arm/arm/cpufunc_asm_armv5.S standard
arm/arm/cpufunc_asm_armv5_ec.S standard
-arm/arm/cpufunc_asm_armv7.S standard
arm/arm/cpufunc_asm_sheeva.S standard
-arm/arm/cpufunc_asm_pj4b.S standard
arm/arm/irq_dispatch.S standard
arm/arm/intr.c standard
arm/mv/bus_space.c standard
arm/mv/common.c standard
arm/mv/gpio.c standard
+arm/mv/ic.c standard
+arm/mv/mv_localbus.c standard
arm/mv/mv_machdep.c standard
arm/mv/mv_pci.c optional pci
arm/mv/mv_sata.c optional ata | atamvsata
@@ -34,6 +32,7 @@ arm/mv/twsi.c optional iicbus
dev/cesa/cesa.c optional cesa
dev/mge/if_mge.c optional mge
+dev/nand/nfc_mv.c optional nand
dev/mvs/mvs_soc.c optional mvs
dev/uart/uart_dev_ns8250.c optional uart
dev/usb/controller/ehci_mv.c optional ehci
Modified: user/jceel/soc2012_armv6/sys/arm/mv/mv_machdep.c
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/mv/mv_machdep.c Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/mv/mv_machdep.c Wed Jun 27 21:47:27 2012 (r237667)
@@ -755,6 +755,7 @@ static struct pmap_devmap fdt_devmap[FDT
{ 0, 0, 0, 0, 0, }
};
+#if 0
static int
platform_sram_devmap(struct pmap_devmap *map)
{
@@ -792,6 +793,7 @@ out:
return (ENOENT);
}
+#endif
/*
* Construct pmap_devmap[] with DT-derived config data.
@@ -800,12 +802,16 @@ static int
platform_devmap_init(void)
{
phandle_t root, child;
- int i;
+ pcell_t bank_count;
+ u_long base, size;
+ int i, num_mapped;
+
+ i = 0;
+ pmap_devmap_bootstrap_table = &fdt_devmap[0];
/*
* IMMR range.
*/
- i = 0;
fdt_devmap[i].pd_va = fdt_immr_va;
fdt_devmap[i].pd_pa = fdt_immr_pa;
fdt_devmap[i].pd_size = fdt_immr_size;
@@ -814,36 +820,54 @@ platform_devmap_init(void)
i++;
/*
- * SRAM range.
- */
- if (i < FDT_DEVMAP_MAX)
- if (platform_sram_devmap(&fdt_devmap[i]) == 0)
- i++;
-
- /*
- * PCI range(s).
+ * PCI range(s) and localbus.
*/
if ((root = OF_finddevice("/")) == -1)
return (ENXIO);
- for (child = OF_child(root); child != 0; child = OF_peer(child))
- if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
+
+ for (child = OF_child(root); child != 0; child = OF_peer(child)) {
+ if (fdt_is_type(child, "pci")) {
/*
* Check space: each PCI node will consume 2 devmap
* entries.
*/
- if (i + 1 >= FDT_DEVMAP_MAX)
+ if (i + 1 >= FDT_DEVMAP_MAX) {
return (ENOMEM);
+ }
/*
* XXX this should account for PCI and multiple ranges
* of a given kind.
*/
- if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
- MV_PCI_VA_MEM_BASE) != 0)
+ if (fdt_pci_devmap(child, &fdt_devmap[i],
+ MV_PCIE_IO_BASE, MV_PCIE_MEM_BASE) != 0)
return (ENXIO);
i += 2;
}
+ if (fdt_is_compatible(child, "mrvl,lbc")) {
+ /* Check available space */
+ if (OF_getprop(child, "bank-count", (void *)&bank_count,
+ sizeof(bank_count)) <= 0)
+ /* If no property, use default value */
+ bank_count = 1;
+ else
+ bank_count = fdt32_to_cpu(bank_count);
+
+ if ((i + bank_count) >= FDT_DEVMAP_MAX)
+ return (ENOMEM);
+
+ /* Add all localbus ranges to device map */
+ num_mapped = 0;
+
+ if (fdt_localbus_devmap(child, &fdt_devmap[i],
+ (int)bank_count, &num_mapped) != 0)
+ return (ENXIO);
+
+ i += num_mapped;
+ }
+ }
+
/*
* CESA SRAM range.
*/
@@ -851,10 +875,26 @@ platform_devmap_init(void)
if (fdt_is_compatible(child, "mrvl,cesa-sram"))
goto moveon;
- pmap_devmap_bootstrap_table = &fdt_devmap[0];
+ if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0)
+ /* No CESA SRAM node. */
+ return (0);
+moveon:
+ if (i >= FDT_DEVMAP_MAX)
+ return (ENOMEM);
+
+ if (fdt_regsize(child, &base, &size) != 0)
+ return (EINVAL);
+
+ fdt_devmap[i].pd_va = MV_CESA_SRAM_BASE; /* XXX */
+ fdt_devmap[i].pd_pa = base;
+ fdt_devmap[i].pd_size = size;
+ fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
+ fdt_devmap[i].pd_cache = PTE_NOCACHE;
+
return (0);
}
+
struct arm32_dma_range *
bus_dma_get_range(void)
{
Modified: user/jceel/soc2012_armv6/sys/arm/mv/mvreg.h
==============================================================================
--- user/jceel/soc2012_armv6/sys/arm/mv/mvreg.h Wed Jun 27 21:35:45 2012 (r237666)
+++ user/jceel/soc2012_armv6/sys/arm/mv/mvreg.h Wed Jun 27 21:47:27 2012 (r237667)
@@ -1,5 +1,5 @@
/*-
- * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
+ * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
* All rights reserved.
*
* Developed by Semihalf.
@@ -49,55 +49,23 @@
#define FIQ_MASK 0x20
#define FIQ_MASK_HI 0x24
#define FIQ_CAUSE_SELECT 0x28
-#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
-#define ENDPOINT_IRQ_MASK(n) 0x30
-#define ENDPOINT_IRQ_MASK_HI(n) 0x34
+#define ENDPOINT_IRQ_MASK_ERROR 0x2C
+#define ENDPOINT_IRQ_MASK 0x30
+#define ENDPOINT_IRQ_MASK_HI 0x34
#define ENDPOINT_IRQ_CAUSE_SELECT 0x38
-#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY)
+#else /* !SOC_MV_DISCOVERY */
#define IRQ_CAUSE 0x0
#define IRQ_MASK 0x4
#define FIQ_MASK 0x8
-#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4)
-#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */
-#define IRQ_MASK_HI (-1) /* interrupt controller code */
-#define FIQ_MASK_HI (-1)
-#define ENDPOINT_IRQ_MASK_HI(n) (-1)
-#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
-#define IRQ_CAUSE_ERROR (-1)
-#define IRQ_MASK_ERROR (-1)
-#elif defined (SOC_MV_ARMADAXP)
-#define IRQ_CAUSE 0x18
-#define IRQ_MASK 0x30
-#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */
-#define IRQ_CAUSE 0x0
-#define IRQ_MASK 0x4
-#define FIQ_MASK 0x8
-#define ENDPOINT_IRQ_MASK(n) 0xC
+#define ENDPOINT_IRQ_MASK 0xC
#define IRQ_CAUSE_HI 0x10
#define IRQ_MASK_HI 0x14
#define FIQ_MASK_HI 0x18
-#define ENDPOINT_IRQ_MASK_HI(n) 0x1C
-#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
+#define ENDPOINT_IRQ_MASK_HI 0x1C
#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */
#define IRQ_MASK_ERROR (-1) /* interrupt controller code */
#endif
-#if defined(SOC_MV_FREY)
-#define BRIDGE_IRQ_CAUSE 0x118
-#define IRQ_TIMER0 0x00000002
-#define IRQ_TIMER1 0x00000004
-#define IRQ_TIMER_WD 0x00000008
-
-#define BRIDGE_IRQ_MASK 0x11c
-#define IRQ_TIMER0_MASK 0x00000002
-#define IRQ_TIMER1_MASK 0x00000004
-#define IRQ_TIMER_WD_MASK 0x00000008
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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