svn commit: r207023 - in user/jmallett/octeon/contrib/binutils: bfd
include/elf include/opcode opcodes
Juli Mallett
jmallett at FreeBSD.org
Wed Apr 21 22:17:26 UTC 2010
Author: jmallett
Date: Wed Apr 21 22:17:25 2010
New Revision: 207023
URL: http://svn.freebsd.org/changeset/base/207023
Log:
Update based on Cavium Octeon SDK 1.7.2 toolchain sources.
Modified:
user/jmallett/octeon/contrib/binutils/bfd/archures.c
user/jmallett/octeon/contrib/binutils/bfd/bfd-in2.h
user/jmallett/octeon/contrib/binutils/bfd/cpu-mips.c
user/jmallett/octeon/contrib/binutils/bfd/elfxx-mips.c
user/jmallett/octeon/contrib/binutils/include/elf/mips.h
user/jmallett/octeon/contrib/binutils/include/opcode/mips.h
user/jmallett/octeon/contrib/binutils/opcodes/mips-dis.c
user/jmallett/octeon/contrib/binutils/opcodes/mips-opc.c
user/jmallett/octeon/contrib/binutils/opcodes/mips16-opc.c
Modified: user/jmallett/octeon/contrib/binutils/bfd/archures.c
==============================================================================
--- user/jmallett/octeon/contrib/binutils/bfd/archures.c Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/bfd/archures.c Wed Apr 21 22:17:25 2010 (r207023)
@@ -1,6 +1,6 @@
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
@@ -18,7 +18,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@@ -141,10 +141,12 @@ DESCRIPTION
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips7000 7000
.#define bfd_mach_mips8000 8000
+.#define bfd_mach_mips9000 9000
.#define bfd_mach_mips10000 10000
.#define bfd_mach_mips12000 12000
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
+.#define bfd_mach_mips_octeon 6502
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
Modified: user/jmallett/octeon/contrib/binutils/bfd/bfd-in2.h
==============================================================================
--- user/jmallett/octeon/contrib/binutils/bfd/bfd-in2.h Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/bfd/bfd-in2.h Wed Apr 21 22:17:25 2010 (r207023)
@@ -8,7 +8,8 @@
/* Main header file for the bfd library -- portable access to object files.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+ Free Software Foundation, Inc.
Contributed by Cygnus Support.
@@ -26,7 +27,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef __BFD_H_SEEN__
#define __BFD_H_SEEN__
Modified: user/jmallett/octeon/contrib/binutils/bfd/cpu-mips.c
==============================================================================
--- user/jmallett/octeon/contrib/binutils/bfd/cpu-mips.c Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/bfd/cpu-mips.c Wed Apr 21 22:17:25 2010 (r207023)
@@ -1,6 +1,6 @@
/* bfd back-end for mips support
Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
- 2002, 2003 Free Software Foundation, Inc.
+ 2002, 2003, 2004 Free Software Foundation, Inc.
Written by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
@@ -17,7 +17,7 @@ GNU General Public License for more deta
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@@ -76,6 +76,7 @@ enum
I_mips6000,
I_mips7000,
I_mips8000,
+ I_mips9000,
I_mips10000,
I_mips12000,
I_mips16,
@@ -84,6 +85,7 @@ enum
I_mipsisa32r2,
I_mipsisa64,
I_mipsisa64r2,
+ I_mipsocteon,
I_sb1,
};
@@ -108,6 +110,7 @@ static const bfd_arch_info_type arch_inf
N (32, 32, bfd_mach_mips6000, "mips:6000", FALSE, NN(I_mips6000)),
N (64, 64, bfd_mach_mips7000, "mips:7000", FALSE, NN(I_mips7000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", FALSE, NN(I_mips8000)),
+ N (64, 64, bfd_mach_mips9000, "mips:9000", FALSE, NN(I_mips9000)),
N (64, 64, bfd_mach_mips10000,"mips:10000", FALSE, NN(I_mips10000)),
N (64, 64, bfd_mach_mips12000,"mips:12000", FALSE, NN(I_mips12000)),
N (64, 64, bfd_mach_mips16, "mips:16", FALSE, NN(I_mips16)),
@@ -116,6 +119,7 @@ static const bfd_arch_info_type arch_inf
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
+ N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
};
Modified: user/jmallett/octeon/contrib/binutils/bfd/elfxx-mips.c
==============================================================================
--- user/jmallett/octeon/contrib/binutils/bfd/elfxx-mips.c Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/bfd/elfxx-mips.c Wed Apr 21 22:17:25 2010 (r207023)
@@ -1,6 +1,6 @@
/* MIPS-specific support for ELF
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
Most of the information added by Ian Lance Taylor, Cygnus Support,
<ian at cygnus.com>.
@@ -23,7 +23,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* This file handles functionality common to the different MIPS ABI's. */
@@ -4088,6 +4088,12 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_5500:
return bfd_mach_mips5500;
+ case E_MIPS_MACH_9000:
+ return bfd_mach_mips9000;
+
+ case E_MIPS_MACH_OCTEON:
+ return bfd_mach_mips_octeon;
+
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
@@ -7142,6 +7148,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
break;
+ case bfd_mach_mips9000:
+ val = E_MIPS_ARCH_4 | E_MIPS_MACH_9000;
+ break;
+
case bfd_mach_mips5000:
case bfd_mach_mips7000:
case bfd_mach_mips8000:
@@ -7154,6 +7164,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_5;
break;
+ case bfd_mach_mips_octeon:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
+ break;
+
case bfd_mach_mips_sb1:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
@@ -8856,6 +8870,9 @@ struct mips_mach_extension {
are ordered topologically with MIPS I extensions listed last. */
static const struct mips_mach_extension mips_mach_extensions[] = {
+ /* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
@@ -8879,6 +8896,7 @@ static const struct mips_mach_extension
{ bfd_mach_mips10000, bfd_mach_mips8000 },
{ bfd_mach_mips5000, bfd_mach_mips8000 },
{ bfd_mach_mips7000, bfd_mach_mips8000 },
+ { bfd_mach_mips9000, bfd_mach_mips8000 },
/* VR4100 extensions. */
{ bfd_mach_mips4120, bfd_mach_mips4100 },
@@ -8913,11 +8931,26 @@ mips_mach_extends_p (unsigned long base,
{
size_t i;
- for (i = 0; extension != base && i < ARRAY_SIZE (mips_mach_extensions); i++)
+ if (extension == base)
+ return TRUE;
+
+ if (base == bfd_mach_mipsisa32
+ && mips_mach_extends_p (bfd_mach_mipsisa64, extension))
+ return TRUE;
+
+ if (base == bfd_mach_mipsisa32r2
+ && mips_mach_extends_p (bfd_mach_mipsisa64r2, extension))
+ return TRUE;
+
+ for (i = 0; i < ARRAY_SIZE (mips_mach_extensions); i++)
if (extension == mips_mach_extensions[i].extension)
- extension = mips_mach_extensions[i].base;
+ {
+ extension = mips_mach_extensions[i].base;
+ if (extension == base)
+ return TRUE;
+ }
- return extension == base;
+ return FALSE;
}
Modified: user/jmallett/octeon/contrib/binutils/include/elf/mips.h
==============================================================================
--- user/jmallett/octeon/contrib/binutils/include/elf/mips.h Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/include/elf/mips.h Wed Apr 21 22:17:25 2010 (r207023)
@@ -1,5 +1,6 @@
/* MIPS ELF support for BFD.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005
Free Software Foundation, Inc.
By Ian Lance Taylor, Cygnus Support, <ian at cygnus.com>, from
@@ -20,7 +21,7 @@ GNU General Public License for more deta
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* This file holds definitions specific to the MIPS ELF ABI. Note
that most of this is not actually implemented by BFD. */
@@ -187,8 +188,10 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4120 0x00870000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
+#define E_MIPS_MACH_OCTEON 0x008b0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
+#define E_MIPS_MACH_9000 0x00990000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
Modified: user/jmallett/octeon/contrib/binutils/include/opcode/mips.h
==============================================================================
--- user/jmallett/octeon/contrib/binutils/include/opcode/mips.h Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/include/opcode/mips.h Wed Apr 21 22:17:25 2010 (r207023)
@@ -1,5 +1,6 @@
/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -18,7 +19,7 @@ the GNU General Public License for more
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _MIPS_H_
#define _MIPS_H_
@@ -89,6 +90,8 @@ Software Foundation, 59 Temple Place - S
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
+#define OP_MASK_BITIND OP_MASK_RT
+#define OP_SH_BITIND OP_SH_RT
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
@@ -147,6 +150,38 @@ Software Foundation, 59 Temple Place - S
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
#define OP_SH_EXTMSBD 11
+/* MIPS DSP ASE */
+#define OP_SH_DSPACC 11
+#define OP_MASK_DSPACC 0x3
+#define OP_SH_DSPACC_S 21
+#define OP_MASK_DSPACC_S 0x3
+#define OP_SH_DSPSFT 20
+#define OP_MASK_DSPSFT 0x3f
+#define OP_SH_DSPSFT_7 19
+#define OP_MASK_DSPSFT_7 0x7f
+#define OP_SH_SA3 21
+#define OP_MASK_SA3 0x7
+#define OP_SH_SA4 21
+#define OP_MASK_SA4 0xf
+#define OP_SH_IMM8 16
+#define OP_MASK_IMM8 0xff
+#define OP_SH_IMM10 16
+#define OP_MASK_IMM10 0x3ff
+#define OP_SH_WRDSP 11
+#define OP_MASK_WRDSP 0x3f
+#define OP_SH_RDDSP 16
+#define OP_MASK_RDDSP 0x3f
+
+/* MIPS MT ASE */
+#define OP_SH_MT_U 5
+#define OP_MASK_MT_U 0x1
+#define OP_SH_MT_H 4
+#define OP_MASK_MT_H 0x1
+#define OP_SH_MTACC_T 18
+#define OP_MASK_MTACC_T 0x3
+#define OP_SH_MTACC_D 13
+#define OP_MASK_MTACC_D 0x3
+
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
@@ -192,6 +227,8 @@ struct mips_opcode
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
+ /* A collection of additional bits describing the instruction. */
+ unsigned long pinfo2;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
@@ -207,6 +244,8 @@ struct mips_opcode
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
+ "^" 5 bit bit index amount (OP_*_BITIND)
+ "~" bit index between 32 and 63, stored after subtracting 32 (OP_*_BITIND)
"a" 26 bit target address (OP_*_TARGET)
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
@@ -231,6 +270,7 @@ struct mips_opcode
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
"J" 19 bit wait function code (OP_*_CODE19)
"x" accept and ignore register name
+ "y" 10 bit signed const (OP_*_CODE2)
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
@@ -293,6 +333,28 @@ struct mips_opcode
"Y" MDMX source register (OP_*_FS)
"Z" MDMX source register (OP_*_FT)
+ DSP ASE usage:
+ "3" 3 bit unsigned immediate (OP_*_SA3)
+ "4" 4 bit unsigned immediate (OP_*_SA4)
+ "5" 8 bit unsigned immediate (OP_*_IMM8)
+ "6" 5 bit unsigned immediate (OP_*_RS)
+ "7" 2 bit dsp accumulator register (OP_*_DSPACC)
+ "8" 6 bit unsigned immediate (OP_*_WRDSP)
+ "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
+ "0" 6 bit signed immediate (OP_*_DSPSFT)
+ ":" 7 bit signed immediate (OP_*_DSPSFT_7)
+ "'" 6 bit unsigned immediate (OP_*_RDDSP)
+ "@" 10 bit signed immediate (OP_*_IMM10)
+
+ MT ASE usage:
+ "!" 1 bit immediate at bit 5
+ "$" 1 bit immediate at bit 4
+ "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
+ "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+ "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+ "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
+ "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -300,13 +362,15 @@ struct mips_opcode
"+" Start of extension sequence.
Characters used so far, for quick reference when adding more:
- "%[]<>(),+"
+ "34567890"
+ "%[]<>(),+:'@!$*&^~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefhijklopqrstuvwxz"
+ "abcdefghijklopqrstuvwxyz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
- "ABCDEFGHI"
+ "ABCDEFGHIT"
+ "t"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -376,10 +440,16 @@ struct mips_opcode
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
-/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
-#define INSN_READ_MDMX_ACC 0
-/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
-#define INSN_WRITE_MDMX_ACC 0
+
+/* These are the bits which may be set in the pinfo2 field of an
+ instruction. */
+
+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
+#define INSN2_ALIAS 0x00000001
+/* Instruction reads MDMX accumulator. */
+#define INSN2_READ_MDMX_ACC 0x00000002
+/* Instruction writes MDMX accumulator. */
+#define INSN2_WRITE_MDMX_ACC 0x00000004
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
@@ -402,8 +472,10 @@ struct mips_opcode
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
-#define INSN_ASE_MASK 0x0000f000
+#define INSN_ASE_MASK 0x0400f000
+/* DSP ASE */
+#define INSN_DSP 0x00001000
/* MIPS 16 ASE */
#define INSN_MIPS16 0x00002000
/* MIPS-3D ASE */
@@ -433,6 +505,10 @@ struct mips_opcode
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+/* MT ASE */
+#define INSN_MT 0x04000000
+/* Cavium Networks Octeon instruction. */
+#define INSN_OCTEON 0x08000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -470,6 +546,7 @@ struct mips_opcode
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
+#define CPU_RM9000 9000
#define CPU_R10000 10000
#define CPU_R12000 12000
#define CPU_MIPS16 16
@@ -479,6 +556,7 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_OCTEON 6502
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -489,12 +567,14 @@ struct mips_opcode
(((insn)->membership & isa) != 0 \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
+ || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
+ || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
@@ -654,6 +734,8 @@ enum
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SAA_AB,
+ M_SAAD_AB,
M_SC_AB,
M_SCD_AB,
M_SD_A,
@@ -857,7 +939,14 @@ extern int bfd_mips_num_opcodes;
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
- */
+ "m" 7 bit register list for save instruction (18 bit extended)
+ "M" 7 bit register list for restore instruction (18 bit extended)
+ */
+
+/* Save/restore encoding for the args field when all 4 registers are
+ either saved as arguments or saved/restored as statics. */
+#define MIPS16_ALL_ARGS 0xe
+#define MIPS16_ALL_STATICS 0xb
/* For the mips16, we use the same opcode table format and a few of
the same flags. However, most of the flags are different. */
Modified: user/jmallett/octeon/contrib/binutils/opcodes/mips-dis.c
==============================================================================
--- user/jmallett/octeon/contrib/binutils/opcodes/mips-dis.c Wed Apr 21 22:16:05 2010 (r207022)
+++ user/jmallett/octeon/contrib/binutils/opcodes/mips-dis.c Wed Apr 21 22:17:25 2010 (r207023)
@@ -1,24 +1,25 @@
/* Print mips instructions for GDB, the GNU debugger, or for objdump.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003
+ 2000, 2001, 2002, 2003, 2005
Free Software Foundation, Inc.
Contributed by Nobuyuki Hikichi(hikichi at sra.co.jp).
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@@ -40,96 +41,95 @@ Foundation, Inc., 59 Temple Place - Suit
/* Mips instructions are at maximum this many bytes long. */
#define INSNLEN 4
-static void set_default_mips_dis_options
- PARAMS ((struct disassemble_info *));
-static void parse_mips_dis_option
- PARAMS ((const char *, unsigned int));
-static void parse_mips_dis_options
- PARAMS ((const char *));
-static int _print_insn_mips
- PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
-static int print_insn_mips
- PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
-static void print_insn_args
- PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
-static int print_insn_mips16
- PARAMS ((bfd_vma, struct disassemble_info *));
-static int is_newabi
- PARAMS ((Elf_Internal_Ehdr *));
-static void print_mips16_insn_arg
- PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
- struct disassemble_info *));
+/* Generate Octeon/MIPS unaligned load and store instructions. */
+#ifdef INCLUDE_OCTEON_USEUN
+int octeon_use_unalign = 1;
+#else
+int octeon_use_unalign = 0;
+#endif
+
/* FIXME: These should be shared with gdb somehow. */
-struct mips_cp0sel_name {
- unsigned int cp0reg;
- unsigned int sel;
- const char * const name;
+struct mips_cp0sel_name
+{
+ unsigned int cp0reg;
+ unsigned int sel;
+ const char * const name;
};
/* The mips16 register names. */
-static const char * const mips16_reg_names[] = {
+static const char * const mips16_reg_names[] =
+{
"s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
};
-static const char * const mips_gpr_names_numeric[32] = {
+static const char * const mips_gpr_names_numeric[32] =
+{
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
-static const char * const mips_gpr_names_oldabi[32] = {
+static const char * const mips_gpr_names_oldabi[32] =
+{
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
-static const char * const mips_gpr_names_newabi[32] = {
+static const char * const mips_gpr_names_newabi[32] =
+{
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
-static const char * const mips_fpr_names_numeric[32] = {
+static const char * const mips_fpr_names_numeric[32] =
+{
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
};
-static const char * const mips_fpr_names_32[32] = {
+static const char * const mips_fpr_names_32[32] =
+{
"fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
"ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
"ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
"fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
};
-static const char * const mips_fpr_names_n32[32] = {
+static const char * const mips_fpr_names_n32[32] =
+{
"fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
"fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
"fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
};
-static const char * const mips_fpr_names_64[32] = {
+static const char * const mips_fpr_names_64[32] =
+{
"fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
"fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
"fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
};
-static const char * const mips_cp0_names_numeric[32] = {
+static const char * const mips_cp0_names_numeric[32] =
+{
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
-static const char * const mips_cp0_names_mips3264[32] = {
+static const char * const mips_cp0_names_mips3264[32] =
+{
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "$7",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
@@ -140,7 +140,8 @@ static const char * const mips_cp0_names
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
-static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
+static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
+{
{ 16, 1, "c0_config1" },
{ 16, 2, "c0_config2" },
{ 16, 3, "c0_config3" },
@@ -172,7 +173,8 @@ static const struct mips_cp0sel_name mip
{ 29, 1, "c0_datahi" }
};
-static const char * const mips_cp0_names_mips3264r2[32] = {
+static const char * const mips_cp0_names_mips3264r2[32] =
+{
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
@@ -183,7 +185,8 @@ static const char * const mips_cp0_names
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
-static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
+static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
+{
{ 4, 1, "c0_contextconfig" },
{ 5, 1, "c0_pagegrain" },
{ 12, 1, "c0_intctl" },
@@ -238,7 +241,8 @@ static const struct mips_cp0sel_name mip
};
/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
-static const char * const mips_cp0_names_sb1[32] = {
+static const char * const mips_cp0_names_sb1[32] =
+{
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "$7",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
@@ -249,7 +253,8 @@ static const char * const mips_cp0_names
"c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
};
-static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
+static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
+{
{ 16, 1, "c0_config1" },
{ 18, 1, "c0_watchlo,1" },
{ 19, 1, "c0_watchhi,1" },
@@ -273,14 +278,46 @@ static const struct mips_cp0sel_name mip
{ 29, 3, "c0_datahi_d" },
};
-static const char * const mips_hwr_names_numeric[32] = {
+static const char * const mips_cp0_names_octeon[32] = {
+ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
+ "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
+ "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
+ "c0_status", "c0_cause", "c0_epc", "c0_prid",
+ "c0_config", "$17", "c0_watchlo", "c0_watchhi",
+ "c0_xcontext", "$21", "c0_mdebug", "c0_debug",
+ "c0_depc", "c0_perfcnt", "$26", "c0_cacheerr",
+ "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
+};
+
+static const struct mips_cp0sel_name mips_cp0sel_names_octeon[] = {
+ { 5, 1, "c0_pagegrain" },
+ { 9, 6, "c0_cvmcount" },
+ { 9, 7, "c0_cvmctl" },
+ { 11, 7, "c0_cvmmemctl" },
+ { 12, 1, "c0_intctl" },
+ { 12, 2, "c0_srsctl" },
+ { 15, 1, "c0_ebase" },
+ { 16, 1, "c0_config1", },
+ { 16, 2, "c0_config2", },
+ { 16, 3, "c0_config3", },
+ { 18, 1, "c0_watchlo,1" },
+ { 19, 1, "c0_watchhi,1" },
+ { 25, 2, "c0_perfcnt,2" },
+ { 27, 1, "c0_cacheerr,1" },
+ { 28, 3, "c0_datalo" },
+ { 29, 3, "c0_datahi" },
+};
+
+static const char * const mips_hwr_names_numeric[32] =
+{
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
-static const char * const mips_hwr_names_mips3264r2[32] = {
+static const char * const mips_hwr_names_mips3264r2[32] =
+{
"hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
"$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
@@ -288,20 +325,23 @@ static const char * const mips_hwr_names
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
-struct mips_abi_choice {
- const char *name;
+struct mips_abi_choice
+{
+ const char * name;
const char * const *gpr_names;
const char * const *fpr_names;
};
-struct mips_abi_choice mips_abi_choices[] = {
+struct mips_abi_choice mips_abi_choices[] =
+{
{ "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
{ "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
{ "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
{ "64", mips_gpr_names_newabi, mips_fpr_names_64 },
};
-struct mips_arch_choice {
+struct mips_arch_choice
+{
const char *name;
int bfd_mach_valid;
unsigned long bfd_mach;
@@ -313,7 +353,8 @@ struct mips_arch_choice {
const char * const *hwr_names;
};
-const struct mips_arch_choice mips_arch_choices[] = {
+const struct mips_arch_choice mips_arch_choices[] =
+{
{ "numeric", 0, 0, 0, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
@@ -366,26 +407,26 @@ const struct mips_arch_choice mips_arch_
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
- ISA_MIPS32 | INSN_MIPS16,
+ ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
- ISA_MIPS32R2 | INSN_MIPS16,
+ ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
- ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
+ ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
- ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
+ ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@@ -396,6 +437,11 @@ const struct mips_arch_choice mips_arch_
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
mips_hwr_names_numeric },
+ { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
+ ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_octeon,
+ mips_cp0sel_names_octeon, ARRAY_SIZE (mips_cp0sel_names_octeon),
+ mips_hwr_names_numeric },
+
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
@@ -414,53 +460,39 @@ static const struct mips_cp0sel_name *mi
static int mips_cp0sel_names_len;
static const char * const *mips_hwr_names;
-static const struct mips_abi_choice *choose_abi_by_name
- PARAMS ((const char *, unsigned int));
-static const struct mips_arch_choice *choose_arch_by_name
- PARAMS ((const char *, unsigned int));
-static const struct mips_arch_choice *choose_arch_by_number
- PARAMS ((unsigned long));
-static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
- PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
- unsigned int));
+/* Other options */
+static int no_aliases; /* If set disassemble as most general inst. */
static const struct mips_abi_choice *
-choose_abi_by_name (name, namelen)
- const char *name;
- unsigned int namelen;
+choose_abi_by_name (const char *name, unsigned int namelen)
{
const struct mips_abi_choice *c;
unsigned int i;
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
- {
- if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
- && strlen (mips_abi_choices[i].name) == namelen)
- c = &mips_abi_choices[i];
- }
+ if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
+ && strlen (mips_abi_choices[i].name) == namelen)
+ c = &mips_abi_choices[i];
+
return c;
}
static const struct mips_arch_choice *
-choose_arch_by_name (name, namelen)
- const char *name;
- unsigned int namelen;
+choose_arch_by_name (const char *name, unsigned int namelen)
{
const struct mips_arch_choice *c = NULL;
unsigned int i;
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
- {
- if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
- && strlen (mips_arch_choices[i].name) == namelen)
- c = &mips_arch_choices[i];
- }
+ if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
+ && strlen (mips_arch_choices[i].name) == namelen)
+ c = &mips_arch_choices[i];
+
return c;
}
static const struct mips_arch_choice *
-choose_arch_by_number (mach)
- unsigned long mach;
+choose_arch_by_number (unsigned long mach)
{
static unsigned long hint_bfd_mach;
static const struct mips_arch_choice *hint_arch_choice;
@@ -487,9 +519,24 @@ choose_arch_by_number (mach)
return c;
}
-void
-set_default_mips_dis_options (info)
- struct disassemble_info *info;
+/* Check if the object uses NewABI conventions. */
+
+static int
+is_newabi (Elf_Internal_Ehdr *header)
+{
+ /* There are no old-style ABIs which use 64-bit ELF. */
+ if (header->e_ident[EI_CLASS] == ELFCLASS64)
+ return 1;
+
+ /* If a 32-bit ELF file, n32 is a new-style ABI. */
+ if ((header->e_flags & EF_MIPS_ABI2) != 0)
+ return 1;
+
+ return 0;
+}
+
+static void
+set_default_mips_dis_options (struct disassemble_info *info)
{
const struct mips_arch_choice *chosen_arch;
@@ -503,6 +550,7 @@ set_default_mips_dis_options (info)
mips_cp0sel_names = NULL;
mips_cp0sel_names_len = 0;
mips_hwr_names = mips_hwr_names_numeric;
+ no_aliases = 0;
/* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
@@ -534,22 +582,37 @@ set_default_mips_dis_options (info)
#endif
}
-void
-parse_mips_dis_option (option, len)
- const char *option;
- unsigned int len;
+static void
+parse_mips_dis_option (const char *option, unsigned int len)
{
unsigned int i, optionlen, vallen;
const char *val;
const struct mips_abi_choice *chosen_abi;
const struct mips_arch_choice *chosen_arch;
- /* Look for the = that delimits the end of the option name. */
- for (i = 0; i < len; i++)
+ if (strcmp ("octeon-useun", option) == 0)
{
- if (option[i] == '=')
- break;
+ octeon_use_unalign = 1;
+ return;
+ }
+ if (strcmp ("no-octeon-useun", option) == 0)
+ {
+ octeon_use_unalign = 0;
+ return;
+ }
+
+ /* Try to match options that are simple flags */
+ if (strncmp (option, "no-aliases", 10) == 0)
+ {
+ no_aliases = 1;
+ return;
}
+
+ /* Look for the = that delimits the end of the option name. */
+ for (i = 0; i < len; i++)
+ if (option[i] == '=')
+ break;
+
if (i == 0) /* Invalid option: no name before '='. */
return;
if (i == len) /* Invalid option: no '='. */
@@ -561,8 +624,8 @@ parse_mips_dis_option (option, len)
val = option + (optionlen + 1);
vallen = len - (optionlen + 1);
- if (strncmp("gpr-names", option, optionlen) == 0
- && strlen("gpr-names") == optionlen)
+ if (strncmp ("gpr-names", option, optionlen) == 0
+ && strlen ("gpr-names") == optionlen)
{
chosen_abi = choose_abi_by_name (val, vallen);
if (chosen_abi != NULL)
@@ -570,8 +633,8 @@ parse_mips_dis_option (option, len)
return;
}
- if (strncmp("fpr-names", option, optionlen) == 0
- && strlen("fpr-names") == optionlen)
+ if (strncmp ("fpr-names", option, optionlen) == 0
+ && strlen ("fpr-names") == optionlen)
{
chosen_abi = choose_abi_by_name (val, vallen);
if (chosen_abi != NULL)
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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