svn commit: r206205 - in user/jmallett/octeon/sys/mips: include mips
Juli Mallett
jmallett at FreeBSD.org
Mon Apr 5 19:25:30 UTC 2010
Author: jmallett
Date: Mon Apr 5 19:25:29 2010
New Revision: 206205
URL: http://svn.freebsd.org/changeset/base/206205
Log:
o) Add an inline function to do a COP0_SYNC.
o) Make intr_disable() just return the IE bit's status.
o) Make intr_restore just do intr_enable if intr_disable returned IE,
rather than spamming the whole status register.
o) Remove some TLB-related macros that are unused and have counterparts
in pte.h now. (XXX They should move to tlb.h.)
o) Use the existing mips_rd_count() inline for get_cyclecount() rather
than having an extern function that does the same thing.
o) Convert everything to intr_disable(), intr_enable() and intr_restore().
o) Remove everything but get_intr_mask and set_intr_mask from psraccess.
o) Add the EntryHi ASID mask to pte.h.
o) Clean up some left-over spam in pmap.c from when I was making the page
directory 32-bit on N64.
o) Remove trapframe->badvaddr modification that was needed to use the old
tlb.S routines.
o) Use COP0_SYNC instead of the less-ambitious HAZARD_DELAY for some mtc0
hazards.
Modified:
user/jmallett/octeon/sys/mips/include/asm.h
user/jmallett/octeon/sys/mips/include/cpu.h
user/jmallett/octeon/sys/mips/include/cpufunc.h
user/jmallett/octeon/sys/mips/include/pte.h
user/jmallett/octeon/sys/mips/include/trap.h
user/jmallett/octeon/sys/mips/mips/exception.S
user/jmallett/octeon/sys/mips/mips/machdep.c
user/jmallett/octeon/sys/mips/mips/mp_machdep.c
user/jmallett/octeon/sys/mips/mips/nexus.c
user/jmallett/octeon/sys/mips/mips/pmap.c
user/jmallett/octeon/sys/mips/mips/psraccess.S
user/jmallett/octeon/sys/mips/mips/tlb.c
user/jmallett/octeon/sys/mips/mips/trap.c
Modified: user/jmallett/octeon/sys/mips/include/asm.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/asm.h Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/include/asm.h Mon Apr 5 19:25:29 2010 (r206205)
@@ -306,28 +306,32 @@ _C_LABEL(x):
/*
* Call ast if required
+ *
+ * XXX Do we really need to disable interrupts?
*/
#define DO_AST \
44: \
- PTR_LA s0, _C_LABEL(disableintr) ;\
- jalr s0 ;\
- nop ;\
- move a0, v0 ;\
+ mfc0 t0, MIPS_COP_0_STATUS ;\
+ and a0, t0, MIPS_SR_INT_IE ;\
+ xor t0, a0, t0 ;\
+ mtc0 t0, MIPS_COP_0_STATUS ;\
+ COP0_SYNC ;\
GET_CPU_PCPU(s1) ;\
PTR_L s3, PC_CURPCB(s1) ;\
PTR_L s1, PC_CURTHREAD(s1) ;\
lw s2, TD_FLAGS(s1) ;\
li s0, TDF_ASTPENDING | TDF_NEEDRESCHED;\
and s2, s0 ;\
- PTR_LA s0, _C_LABEL(restoreintr) ;\
- jalr s0 ;\
- nop ;\
+ mfc0 t0, MIPS_COP_0_STATUS ;\
+ or t0, a0, t0 ;\
+ mtc0 t0, MIPS_COP_0_STATUS ;\
+ COP0_SYNC ;\
beq s2, zero, 4f ;\
nop ;\
PTR_LA s0, _C_LABEL(ast) ;\
jalr s0 ;\
PTR_ADDU a0, s3, U_PCB_REGS ;\
- j 44b ;\
+ j 44b ;\
nop ;\
4:
Modified: user/jmallett/octeon/sys/mips/include/cpu.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpu.h Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/include/cpu.h Mon Apr 5 19:25:29 2010 (r206205)
@@ -275,27 +275,6 @@
#define OPCODE_C1 0x11
/*
- * The low part of the TLB entry.
- */
-#define VMTLB_PF_NUM 0x3fffffc0
-#define VMTLB_ATTR_MASK 0x00000038
-#define VMTLB_MOD_BIT 0x00000004
-#define VMTLB_VALID_BIT 0x00000002
-#define VMTLB_GLOBAL_BIT 0x00000001
-
-#define VMTLB_PHYS_PAGE_SHIFT 6
-
-/*
- * The high part of the TLB entry.
- */
-#define VMTLB_VIRT_PAGE_NUM 0xffffe000
-#define VMTLB_PID 0x000000ff
-#define VMTLB_PID_R9K 0x00000fff
-#define VMTLB_PID_SHIFT 0
-#define VMTLB_VIRT_PAGE_SHIFT 12
-#define VMTLB_VIRT_PAGE_SHIFT_R9K 13
-
-/*
* The first TLB entry that write random hits.
* TLB entry 0 maps the kernel stack of the currently running thread
* TLB entry 1 maps the pcpu area of processor (only for SMP builds)
@@ -314,14 +293,6 @@
#define VMNUM_PIDS 256
/*
- * TLB probe return codes.
- */
-#define VMTLB_NOT_FOUND 0
-#define VMTLB_FOUND 1
-#define VMTLB_FOUND_WITH_PATCH 2
-#define VMTLB_PROBE_ERROR 3
-
-/*
* Exported definitions unique to mips cpu support.
*/
@@ -334,7 +305,9 @@
#define cpu_swapout(p) panic("cpu_swapout: can't get here");
#ifndef _LOCORE
+#include <machine/cpufunc.h>
#include <machine/frame.h>
+
/*
* Arguments to hardclock and gatherstats encapsulate the previous
* machine state in an opaque clockframe.
@@ -351,6 +324,11 @@
#define cpu_getstack(td) ((td)->td_frame->sp)
/*
+ * A machine-independent interface to the CPU's counter.
+ */
+#define get_cyclecount() mips_rd_count()
+
+/*
* CPU identification, from PRID register.
*/
union cpuprid {
@@ -453,7 +431,6 @@ extern union cpuprid fpu_id;
struct user;
-u_int32_t mips_cp0_config1_read(void);
int Mips_ConfigCache(void);
void Mips_SyncCache(void);
@@ -520,23 +497,12 @@ extern int intr_nesting_level;
* Low level access routines to CPU registers
*/
-void setsoftintr0(void);
-void clearsoftintr0(void);
-void setsoftintr1(void);
-void clearsoftintr1(void);
-
-
-int disableintr(void);
-void restoreintr(int);
-int enableintr(void);
-
void swi_vm(void *);
void cpu_halt(void);
void cpu_reset(void);
u_int32_t set_intr_mask(u_int32_t);
u_int32_t get_intr_mask(void);
-u_int32_t get_cyclecount(void);
#define cpu_spinwait() /* nothing */
Modified: user/jmallett/octeon/sys/mips/include/cpufunc.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpufunc.h Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/include/cpufunc.h Mon Apr 5 19:25:29 2010 (r206205)
@@ -83,6 +83,12 @@ mips_barrier(void)
}
static __inline void
+mips_cp0_sync(void)
+{
+ __asm __volatile (__XSTRING(COP0_SYNC));
+}
+
+static __inline void
mips_wbflush(void)
{
__asm __volatile ("sync" : : : "memory");
@@ -237,7 +243,7 @@ intr_disable(void)
s = mips_rd_status();
mips_wr_status(s & ~MIPS_SR_INT_IE);
- return (s);
+ return (s & MIPS_SR_INT_IE);
}
static __inline register_t
@@ -251,7 +257,13 @@ intr_enable(void)
return (s);
}
-#define intr_restore(s) mips_wr_status((s))
+static __inline void
+intr_restore(register_t ie)
+{
+ if (ie == MIPS_SR_INT_IE) {
+ intr_enable();
+ }
+}
static __inline void
breakpoint(void)
Modified: user/jmallett/octeon/sys/mips/include/pte.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/pte.h Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/include/pte.h Mon Apr 5 19:25:29 2010 (r206205)
@@ -89,6 +89,7 @@ typedef pt_entry_t *pd_entry_t;
*
* Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
*/
+#define TLBHI_ASID_MASK (0xff)
#if defined(__mips_n64)
#define TLBHI_R_SHIFT 62
#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT)
@@ -102,9 +103,9 @@ typedef pt_entry_t *pd_entry_t;
#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK)
#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \
(TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
- ((asid)))
+ ((asid) & TLBHI_ASID_MASK))
#else
-#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | (asid))
+#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
#endif
/*
Modified: user/jmallett/octeon/sys/mips/include/trap.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/trap.h Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/include/trap.h Mon Apr 5 19:25:29 2010 (r206205)
@@ -84,7 +84,7 @@ struct trapdebug { /* trap history buff
};
#define trapdebug_enter(x, cd) { \
- intrmask_t s = disableintr(); \
+ register_t s = intr_disable(); \
trp->status = x->sr; \
trp->cause = x->cause; \
trp->vadr = x->badvaddr; \
@@ -94,7 +94,7 @@ struct trapdebug { /* trap history buff
trp->code = cd; \
if (++trp == &trapdebug[TRAPSIZE]) \
trp = trapdebug; \
- restoreintr(s); \
+ intr_restore(s); \
}
#define TRAPSIZE 10 /* Trap log buffer length */
Modified: user/jmallett/octeon/sys/mips/mips/exception.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/exception.S Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/exception.S Mon Apr 5 19:25:29 2010 (r206205)
@@ -151,10 +151,10 @@ MipsDoTLBMiss:
lw k0, 0(k1) #0e: k0=lo0 pte
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded
- HAZARD_DELAY
+ COP0_SYNC
addu k0, TLBLO_PFN_ODD
MTC0 k0, COP_0_TLB_LO1 #15: lo1 is loaded
- HAZARD_DELAY
+ COP0_SYNC
tlbwr #1a: write to tlb
HAZARD_DELAY
eret #1f: retUrn from exception
@@ -861,15 +861,14 @@ NLEAF(MipsTLBInvalidException)
lw k0, 0(k1)
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0
- HAZARD_DELAY
+ COP0_SYNC
addu k0, TLBLO_PFN_ODD
MTC0 k0, COP_0_TLB_LO1
- HAZARD_DELAY
+ COP0_SYNC
tlbp
HAZARD_DELAY
mfc0 k0, COP_0_TLB_INDEX
- HAZARD_DELAY
bltz k0, tlb_insert_random
nop
tlbwi
@@ -1002,10 +1001,10 @@ NLEAF(MipsTLBMissException)
lw k0, 0(k1) # k0=lo0 pte
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded
- HAZARD_DELAY
+ COP0_SYNC
addu k0, TLBLO_PFN_ODD
MTC0 k0, COP_0_TLB_LO1 # lo1 is loaded
- HAZARD_DELAY
+ COP0_SYNC
tlbwr # write to tlb
HAZARD_DELAY
eret # return from exception
@@ -1179,7 +1178,7 @@ NESTED_NOPROFILE(MipsCacheException, KER
li k1, SR_DIAG_DE # ignore further errors
or k0, k1
mtc0 k0, COP_0_STATUS_REG # restore status
- HAZARD_DELAY
+ COP0_SYNC
eret
Modified: user/jmallett/octeon/sys/mips/mips/machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/machdep.c Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/machdep.c Mon Apr 5 19:25:29 2010 (r206205)
@@ -373,7 +373,7 @@ mips_vector_init(void)
* when handler is installed for it
*/
set_intr_mask(ALL_INT_MASK);
- enableintr();
+ intr_enable();
/* Clear BEV in SR so we start handling our own exceptions */
mips_wr_status(mips_rd_status() & ~SR_BOOT_EXC_VEC);
@@ -474,7 +474,7 @@ spinlock_enter(void)
td = curthread;
if (td->td_md.md_spinlock_count == 0)
- td->td_md.md_saved_intr = disableintr();
+ td->td_md.md_saved_intr = intr_disable();
td->td_md.md_spinlock_count++;
critical_enter();
}
@@ -488,16 +488,7 @@ spinlock_exit(void)
critical_exit();
td->td_md.md_spinlock_count--;
if (td->td_md.md_spinlock_count == 0)
- restoreintr(td->td_md.md_saved_intr);
-}
-
-u_int32_t
-get_cyclecount(void)
-{
- u_int32_t count;
-
- mfc0_macro(count, 9);
- return (count);
+ intr_restore(td->td_md.md_saved_intr);
}
/*
Modified: user/jmallett/octeon/sys/mips/mips/mp_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mp_machdep.c Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/mp_machdep.c Mon Apr 5 19:25:29 2010 (r206205)
@@ -245,7 +245,7 @@ smp_init_secondary(u_int32_t cpuid)
mips_dcache_wbinv_all();
mips_icache_sync_all();
- mips_wr_entryhi(0 << VMTLB_PID_SHIFT);
+ mips_wr_entryhi(0);
pcpu_init(PCPU_ADDR(cpuid), cpuid, sizeof(struct pcpu));
dpcpu_init(dpcpu, cpuid);
Modified: user/jmallett/octeon/sys/mips/mips/nexus.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/nexus.c Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/nexus.c Mon Apr 5 19:25:29 2010 (r206205)
@@ -166,16 +166,19 @@ static int
nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
{
+ register_t s;
int irq;
- intrmask_t s = disableintr();
+ s = intr_disable();
irq = rman_get_start(res);
- if (irq >= NUM_MIPS_IRQS)
+ if (irq >= NUM_MIPS_IRQS) {
+ intr_restore(s);
return (0);
+ }
cpu_establish_hardintr(device_get_nameunit(child), filt, intr, arg,
irq, flags, cookiep);
- restoreintr(s);
+ intr_restore(s);
return (0);
}
Modified: user/jmallett/octeon/sys/mips/mips/pmap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/pmap.c Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/pmap.c Mon Apr 5 19:25:29 2010 (r206205)
@@ -213,7 +213,7 @@ pt_entry_t *
pmap_segmap(pmap_t pmap, vm_offset_t va)
{
if (pmap->pm_segtab)
- return ((pt_entry_t *)(intptr_t)*pmap_pde(pmap, va));
+ return (*pmap_pde(pmap, va));
else
return ((pd_entry_t)0);
}
@@ -445,7 +445,7 @@ again:
* level page table.
*/
for (i = 0, j = pmap_segshift(virtual_avail); i < nkpt; i++, j++)
- kernel_segmap[j] = (pd_entry_t)(intptr_t)(pgtab + (i * NPTEPG));
+ kernel_segmap[j] = pgtab + (i * NPTEPG);
/*
* The kernel's pmap is statically allocated so we don't have to use
@@ -459,7 +459,7 @@ again:
kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
kernel_pmap->pm_asid[0].gen = 0;
pmap_max_asid = VMNUM_PIDS;
- mips_wr_entryhi(0 << VMTLB_PID_SHIFT);
+ mips_wr_entryhi(0);
}
/*
@@ -2146,7 +2146,7 @@ pmap_kenter_temporary(vm_paddr_t pa, int
{
vm_offset_t va;
#if !defined(__mips_n64)
- int int_level;
+ register_t intr;
#endif
if (i != 0)
printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
@@ -2171,7 +2171,7 @@ pmap_kenter_temporary(vm_paddr_t pa, int
* we get to this point, we might want to consider this (leaving things
* disabled as a starting point ;-)
*/
- int_level = disableintr();
+ intr = intr_disable();
cpu = PCPU_GET(cpuid);
sysm = &sysmap_lmem[cpu];
/* Since this is for the debugger, no locks or any other fun */
@@ -2179,7 +2179,7 @@ pmap_kenter_temporary(vm_paddr_t pa, int
sysm->valid1 = 1;
pmap_update_page(kernel_pmap, (vm_offset_t)sysm->CADDR1, sysm->CMAP1);
va = (vm_offset_t)sysm->CADDR1;
- restoreintr(int_level);
+ intr_restore(intr);
}
#endif
return ((void *)va);
@@ -2190,7 +2190,7 @@ pmap_kenter_temporary_free(vm_paddr_t pa
{
#if !defined(__mips_n64)
int cpu;
- int int_level;
+ register_t intr;
struct local_sysmaps *sysm;
if (pa < MIPS_KSEG0_LARGEST_PHYS) {
@@ -2200,9 +2200,9 @@ pmap_kenter_temporary_free(vm_paddr_t pa
cpu = PCPU_GET(cpuid);
sysm = &sysmap_lmem[cpu];
if (sysm->valid1) {
- int_level = disableintr();
+ intr = intr_disable();
pmap_invalidate_page(kernel_pmap, (vm_offset_t)sysm->CADDR1);
- restoreintr(int_level);
+ intr_restore(intr);
sysm->CMAP1 = 0;
sysm->valid1 = 0;
}
@@ -2316,7 +2316,7 @@ pmap_zero_page(vm_page_t m)
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
#if !defined(__mips_n64)
- int int_level;
+ register_t intr;
#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
@@ -2360,13 +2360,13 @@ pmap_zero_page(vm_page_t m)
sysm = &sysmap_lmem[cpu];
PMAP_LGMEM_LOCK(sysm);
sched_pin();
- int_level = disableintr();
+ intr = intr_disable();
sysm->CMAP1 = TLBLO_PA_TO_PFN(phys) | PG_D | PG_V | PG_G | PG_W | PG_C_CNC;
sysm->valid1 = 1;
pmap_update_page(kernel_pmap, (vm_offset_t)sysm->CADDR1, sysm->CMAP1);
bzero(sysm->CADDR1, PAGE_SIZE);
pmap_invalidate_page(kernel_pmap, (vm_offset_t)sysm->CADDR1);
- restoreintr(int_level);
+ intr_restore(intr);
sysm->CMAP1 = 0;
sysm->valid1 = 0;
sched_unpin();
@@ -2387,7 +2387,7 @@ pmap_zero_page_area(vm_page_t m, int off
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
#if !defined(__mips_n64)
- int int_level;
+ register_t intr;
#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
@@ -2425,14 +2425,14 @@ pmap_zero_page_area(vm_page_t m, int off
cpu = PCPU_GET(cpuid);
sysm = &sysmap_lmem[cpu];
PMAP_LGMEM_LOCK(sysm);
- int_level = disableintr();
+ intr = intr_disable();
sched_pin();
sysm->CMAP1 = TLBLO_PA_TO_PFN(phys) | PG_D | PG_V | PG_G | PG_W | PG_C_CNC;
sysm->valid1 = 1;
pmap_update_page(kernel_pmap, (vm_offset_t)sysm->CADDR1, sysm->CMAP1);
bzero((char *)sysm->CADDR1 + off, size);
pmap_invalidate_page(kernel_pmap, (vm_offset_t)sysm->CADDR1);
- restoreintr(int_level);
+ intr_restore(intr);
sysm->CMAP1 = 0;
sysm->valid1 = 0;
sched_unpin();
@@ -2447,7 +2447,7 @@ pmap_zero_page_idle(vm_page_t m)
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
#if !defined(__mips_n64)
- int int_level;
+ register_t intr;
#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
@@ -2476,14 +2476,14 @@ pmap_zero_page_idle(vm_page_t m)
cpu = PCPU_GET(cpuid);
sysm = &sysmap_lmem[cpu];
PMAP_LGMEM_LOCK(sysm);
- int_level = disableintr();
+ intr = intr_disable();
sched_pin();
sysm->CMAP1 = TLBLO_PA_TO_PFN(phys) | PG_D | PG_V | PG_G | PG_W | PG_C_CNC;
sysm->valid1 = 1;
pmap_update_page(kernel_pmap, (vm_offset_t)sysm->CADDR1, sysm->CMAP1);
bzero(sysm->CADDR1, PAGE_SIZE);
pmap_invalidate_page(kernel_pmap, (vm_offset_t)sysm->CADDR1);
- restoreintr(int_level);
+ intr_restore(intr);
sysm->CMAP1 = 0;
sysm->valid1 = 0;
sched_unpin();
@@ -2505,7 +2505,7 @@ pmap_copy_page(vm_page_t src, vm_page_t
vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src);
vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst);
#if !defined(__mips_n64)
- int int_level;
+ register_t intr;
#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
@@ -2564,7 +2564,7 @@ pmap_copy_page(vm_page_t src, vm_page_t
sysm = &sysmap_lmem[cpu];
PMAP_LGMEM_LOCK(sysm);
sched_pin();
- int_level = disableintr();
+ intr = intr_disable();
if (phy_src < MIPS_KSEG0_LARGEST_PHYS) {
/* one side needs mapping - dest */
va_src = MIPS_PHYS_TO_KSEG0(phy_src);
@@ -2600,7 +2600,7 @@ pmap_copy_page(vm_page_t src, vm_page_t
sysm->CMAP2 = 0;
sysm->valid2 = 0;
}
- restoreintr(int_level);
+ intr_restore(intr);
sched_unpin();
PMAP_LGMEM_UNLOCK(sysm);
}
@@ -3058,7 +3058,7 @@ pmap_activate(struct thread *td)
pmap_asid_alloc(pmap);
if (td == curthread) {
PCPU_SET(segbase, pmap->pm_segtab);
- mips_wr_entryhi(pmap->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT);
+ mips_wr_entryhi(pmap->pm_asid[PCPU_GET(cpuid)].asid);
}
PCPU_SET(curpmap, pmap);
Modified: user/jmallett/octeon/sys/mips/mips/psraccess.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/psraccess.S Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/psraccess.S Mon Apr 5 19:25:29 2010 (r206205)
@@ -53,109 +53,6 @@
.set noreorder # Noreorder is default style!
-/*
- * Set/clear software interrupt.
- */
-
-LEAF(setsoftintr0)
- mfc0 v0, COP_0_CAUSE_REG # read cause register
- nop
- or v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt
- mtc0 v0, COP_0_CAUSE_REG # save it
- j ra
- nop
-END(setsoftintr0)
-
-LEAF(clearsoftintr0)
- mfc0 v0, COP_0_CAUSE_REG # read cause register
- nop
- and v0, v0, ~SOFT_INT_MASK_0 # clear soft clock interrupt
- mtc0 v0, COP_0_CAUSE_REG # save it
- j ra
- nop
-END(clearsoftintr0)
-
-LEAF(setsoftintr1)
- mfc0 v0, COP_0_CAUSE_REG # read cause register
- nop
- or v0, v0, SOFT_INT_MASK_1 # set soft net interrupt
- mtc0 v0, COP_0_CAUSE_REG # save it
- j ra
- nop
-END(setsoftintr1)
-
-LEAF(clearsoftintr1)
- mfc0 v0, COP_0_CAUSE_REG # read cause register
- nop
- and v0, v0, ~SOFT_INT_MASK_1 # clear soft net interrupt
- mtc0 v0, COP_0_CAUSE_REG # save it
- j ra
- nop
-END(clearsoftintr1)
-
-/*
- * Set/change interrupt priority routines.
- * These routines return the previous state.
- */
-LEAF(restoreintr)
- mfc0 t0,COP_0_STATUS_REG
- and t1,t0,SR_INT_ENAB
- beq a0,t1,1f
- xor t0,SR_INT_ENAB
-
- .set noreorder
-
- mtc0 t0,COP_0_STATUS_REG
- nop
- nop
- nop
- nop
-1:
- j ra
- nop
-END(restoreintr)
-
-/*
- * Set/change interrupt priority routines.
- * These routines return the previous state.
- */
-
-LEAF(enableintr)
-#ifdef TARGET_OCTEON
- .set mips64r2
- ei v0
- and v0, SR_INT_ENAB # return old interrupt enable bit
- .set mips0
-#else
- mfc0 v0, COP_0_STATUS_REG # read status register
- nop
- or v1, v0, SR_INT_ENAB
- mtc0 v1, COP_0_STATUS_REG # enable all interrupts
- and v0, SR_INT_ENAB # return old interrupt enable
-#endif
- j ra
- nop
-END(enableintr)
-
-
-LEAF(disableintr)
-#ifdef TARGET_OCTEON
- .set mips64r2
- di v0
- and v0, SR_INT_ENAB # return old interrupt enable bit
- .set mips0
-#else
- mfc0 v0, COP_0_STATUS_REG # read status register
- nop
- and v1, v0, ~SR_INT_ENAB
- mtc0 v1, COP_0_STATUS_REG # disable all interrupts
- MIPS_CPU_NOP_DELAY
- and v0, SR_INT_ENAB # return old interrupt enable
-#endif
- j ra
- nop
-END(disableintr)
-
LEAF(set_intr_mask)
li t0, SR_INT_MASK # 1 means masked so invert.
not a0, a0 # 1 means masked so invert.
@@ -182,17 +79,3 @@ LEAF(get_intr_mask)
nop
END(get_intr_mask)
-
-/*
- * u_int32_t mips_cp0_config1_read(void)
- *
- * Return the current value of the CP0 Config (Select 1) register.
- */
-LEAF(mips_cp0_config1_read)
- .set push
- .set mips32
- mfc0 v0, COP_0_CONFIG, 1
- j ra
- nop
- .set pop
-END(mips_cp0_config1_read)
Modified: user/jmallett/octeon/sys/mips/mips/tlb.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/tlb.c Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/tlb.c Mon Apr 5 19:25:29 2010 (r206205)
@@ -167,8 +167,8 @@ DB_SHOW_COMMAND(tlb, ddb_dump_tlb)
continue;
db_printf("#%u\t=> %jx\n", i, (intmax_t)ehi);
- db_printf(" Lo0\t%jx\n", (intmax_t)elo0);
- db_printf(" Lo1\t%jx\n", (intmax_t)elo1);
+ db_printf(" Lo0\t%jx\t(%#jx)\n", (intmax_t)elo0, (intmax_t)TLBLO_PTE_TO_PA(elo0));
+ db_printf(" Lo1\t%jx\t(%#jx)\n", (intmax_t)elo1, (intmax_t)TLBLO_PTE_TO_PA(elo1));
}
db_printf("Finished.\n");
}
Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c Mon Apr 5 18:46:29 2010 (r206204)
+++ user/jmallett/octeon/sys/mips/mips/trap.c Mon Apr 5 19:25:29 2010 (r206205)
@@ -307,9 +307,9 @@ trap(struct trapframe *trapframe)
*/
if (trapframe->sr & SR_INT_ENAB) {
set_intr_mask(~(trapframe->sr & ALL_INT_MASK));
- enableintr();
+ intr_enable();
} else {
- disableintr();
+ intr_disable();
}
#ifdef TRAP_DEBUG
@@ -330,7 +330,7 @@ trap(struct trapframe *trapframe)
#ifdef SMP
printf("cpuid = %d\n", PCPU_GET(cpuid));
#endif
- pid = mips_rd_entryhi() & VMTLB_PID;
+ pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
(intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
(intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
@@ -383,7 +383,6 @@ trap(struct trapframe *trapframe)
#ifdef SMP
/* It is possible that some other CPU changed m-bit */
if (!pte_test(pte, PG_V) || pte_test(pte, PG_D)) {
- trapframe->badvaddr &= ~PAGE_MASK;
pmap_update_page(kernel_pmap,
trapframe->badvaddr, *pte);
PMAP_UNLOCK(kernel_pmap);
@@ -400,7 +399,6 @@ trap(struct trapframe *trapframe)
goto kernel_fault;
}
pte_set(pte, PG_D);
- trapframe->badvaddr &= ~PAGE_MASK;
pmap_update_page(kernel_pmap, trapframe->badvaddr, *pte);
pa = TLBLO_PTE_TO_PA(*pte);
if (!page_is_managed(pa))
@@ -424,7 +422,6 @@ trap(struct trapframe *trapframe)
#ifdef SMP
/* It is possible that some other CPU changed m-bit */
if (!pte_test(pte, PG_V) || pte_test(pte, PG_D)) {
- trapframe->badvaddr = (trapframe->badvaddr & ~PAGE_MASK);
pmap_update_page(pmap, trapframe->badvaddr, entry);
PMAP_UNLOCK(pmap);
goto out;
@@ -441,9 +438,7 @@ trap(struct trapframe *trapframe)
goto dofault;
}
pte_set(pte, PG_D);
- trapframe->badvaddr = (trapframe->badvaddr & ~PAGE_MASK);
pmap_update_page(pmap, trapframe->badvaddr, *pte);
- trapframe->badvaddr |= (pmap->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT);
pa = TLBLO_PTE_TO_PA(*pte);
if (!page_is_managed(pa))
panic("trap: utlbmod: unmanaged page");
@@ -1033,9 +1028,10 @@ out:
void
trapDump(char *msg)
{
- int i, s;
+ register_t s;
+ int i;
- s = disableintr();
+ s = intr_disable();
printf("trapDump(%s)\n", msg);
for (i = 0; i < TRAPSIZE; i++) {
if (trp == trapdebug) {
@@ -1053,7 +1049,7 @@ trapDump(char *msg)
printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra, (intmax_t)trp->sp, (int)trp->code);
}
- restoreintr(s);
+ intr_restore(s);
}
#endif
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