svn commit: r333203 - stable/10/sys/dev/usb/controller

[Hans Petter Selasky]

Author: hselasky
Date: Thu May  3 07:38:45 2018
New Revision: 333203
URL: https://svnweb.freebsd.org/changeset/base/333203

Log:
  MFC r333100:
  Improve fix in r304629 by allowing configuration of the behaviour
  through a SYSCTL instead of a compile time define.
  
  Add quirk by default for all LynxPoint XHCI controllers.
  
  PR:		227602
  Sponsored by:	Mellanox Technologies

Modified:
  stable/10/sys/dev/usb/controller/xhci.c
  stable/10/sys/dev/usb/controller/xhci.h
  stable/10/sys/dev/usb/controller/xhci_pci.c
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/dev/usb/controller/xhci.c
==============================================================================
--- stable/10/sys/dev/usb/controller/xhci.c	Thu May  3 07:37:49 2018	(r333202)
+++ stable/10/sys/dev/usb/controller/xhci.c	Thu May  3 07:38:45 2018	(r333203)
@@ -99,6 +99,7 @@ static int xhcidebug;
 static int xhciroute;
 static int xhcipolling;
 static int xhcidma32;
+static int xhcictlstep;
 
 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
     &xhcidebug, 0, "Debug level");
@@ -112,9 +113,13 @@ TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
+SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
+    &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
+TUNABLE_INT("hw.usb.xhci.ctlstep", &xhcictlstep);
 #else
 #define	xhciroute 0
 #define	xhcidma32 0
+#define	xhcictlstep 0
 #endif
 
 #define	XHCI_INTR_ENDPT 1
@@ -2244,11 +2249,17 @@ xhci_setup_generic_chain(struct usb_xfer *xfer)
 		 * Send a DATA1 message and invert the current
 		 * endpoint direction.
 		 */
-#ifdef XHCI_STEP_STATUS_STAGE
-		temp.step_td = (xfer->nframes != 0);
-#else
-		temp.step_td = 0;
-#endif
+		if (xhcictlstep || temp.sc->sc_ctlstep) {
+			/*
+			 * Some XHCI controllers will not delay the
+			 * status stage until the next SOF. Force this
+			 * behaviour to avoid failed control
+			 * transfers.
+			 */
+			temp.step_td = (xfer->nframes != 0);
+		} else {
+			temp.step_td = 0;
+		}
 		temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
 		temp.len = 0;
 		temp.pc = NULL;

Modified: stable/10/sys/dev/usb/controller/xhci.h
==============================================================================
--- stable/10/sys/dev/usb/controller/xhci.h	Thu May  3 07:37:49 2018	(r333202)
+++ stable/10/sys/dev/usb/controller/xhci.h	Thu May  3 07:38:45 2018	(r333203)
@@ -506,6 +506,8 @@ struct xhci_softc {
 	uint8_t			sc_noport;
 	/* root HUB device configuration */
 	uint8_t			sc_conf;
+	/* step status stage of all control transfers */
+	uint8_t			sc_ctlstep;
 	/* root HUB port event bitmap, max 256 ports */
 	uint8_t			sc_hub_idata[32];
 

Modified: stable/10/sys/dev/usb/controller/xhci_pci.c
==============================================================================
--- stable/10/sys/dev/usb/controller/xhci_pci.c	Thu May  3 07:37:49 2018	(r333202)
+++ stable/10/sys/dev/usb/controller/xhci_pci.c	Thu May  3 07:38:45 2018	(r333203)
@@ -240,6 +240,7 @@ xhci_pci_attach(device_t self)
 		 */
 		sc->sc_port_route = &xhci_pci_port_route;
 		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
+		sc->sc_ctlstep = 1;
 		break;
 	}