svn commit: r336161 - in stable/11: lib/libvmmapi usr.sbin/bhyve
Marcelo Araujo
araujo at FreeBSD.org
Tue Jul 10 04:26:36 UTC 2018
Author: araujo
Date: Tue Jul 10 04:26:32 2018
New Revision: 336161
URL: https://svnweb.freebsd.org/changeset/base/336161
Log:
MFC r334307, r335103-r335104
r334307:
Simplify macros EFPRINTF and EFFLUSH. [0]
Also stdarg(3) says that each invocation of va_start() must be paired
with a corresponding invocation of va_end() in the same function. [1]
Reported by: Coverity
CID: 1194318[0] and 1194332[1]
Discussed with: jhb
Sponsored by: iXsystems Inc.
Differential Revision: https://reviews.freebsd.org/D15548
r335103:
Fix style(9) space vs tab.
Reviewed by: jhb
Sponsored by: iXsystems Inc.
Differential Revision: https://reviews.freebsd.org/D15774
r335104:
Fix style(9) space vs tab.
Reviewed by: jhb
Sponsored by: iXsystems Inc.
Differential Revision: https://reviews.freebsd.org/D15768
Modified:
stable/11/lib/libvmmapi/vmmapi.c
stable/11/usr.sbin/bhyve/acpi.c
stable/11/usr.sbin/bhyve/ahci.h
stable/11/usr.sbin/bhyve/bhyverun.c
stable/11/usr.sbin/bhyve/block_if.c
stable/11/usr.sbin/bhyve/bootrom.h
stable/11/usr.sbin/bhyve/console.h
stable/11/usr.sbin/bhyve/consport.c
stable/11/usr.sbin/bhyve/inout.c
stable/11/usr.sbin/bhyve/mem.h
stable/11/usr.sbin/bhyve/mevent.c
stable/11/usr.sbin/bhyve/mevent_test.c
stable/11/usr.sbin/bhyve/pci_e82545.c
stable/11/usr.sbin/bhyve/pci_emul.c
stable/11/usr.sbin/bhyve/pci_virtio_net.c
stable/11/usr.sbin/bhyve/pci_xhci.c
stable/11/usr.sbin/bhyve/rfb.c
stable/11/usr.sbin/bhyve/rtc.c
stable/11/usr.sbin/bhyve/sockstream.c
stable/11/usr.sbin/bhyve/uart_emul.c
stable/11/usr.sbin/bhyve/usb_mouse.c
stable/11/usr.sbin/bhyve/vga.h
stable/11/usr.sbin/bhyve/virtio.c
stable/11/usr.sbin/bhyve/virtio.h
Directory Properties:
stable/11/ (props changed)
Modified: stable/11/lib/libvmmapi/vmmapi.c
==============================================================================
--- stable/11/lib/libvmmapi/vmmapi.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/lib/libvmmapi/vmmapi.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -83,19 +83,19 @@ struct vmctx {
static int
vm_device_open(const char *name)
{
- int fd, len;
- char *vmfile;
+ int fd, len;
+ char *vmfile;
len = strlen("/dev/vmm/") + strlen(name) + 1;
vmfile = malloc(len);
assert(vmfile != NULL);
snprintf(vmfile, len, "/dev/vmm/%s", name);
- /* Open the device file */
- fd = open(vmfile, O_RDWR, 0);
+ /* Open the device file */
+ fd = open(vmfile, O_RDWR, 0);
free(vmfile);
- return (fd);
+ return (fd);
}
int
@@ -840,7 +840,7 @@ vm_set_capability(struct vmctx *ctx, int vcpu, enum vm
vmcap.cpuid = vcpu;
vmcap.captype = cap;
vmcap.capval = val;
-
+
return (ioctl(ctx->fd, VM_SET_CAPABILITY, &vmcap));
}
@@ -1457,4 +1457,3 @@ vm_get_ioctls(size_t *len)
*len = nitems(vm_ioctl_cmds);
return (NULL);
}
-
Modified: stable/11/usr.sbin/bhyve/acpi.c
==============================================================================
--- stable/11/usr.sbin/bhyve/acpi.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/acpi.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -118,18 +118,14 @@ struct basl_fio {
};
#define EFPRINTF(...) \
- err = fprintf(__VA_ARGS__); if (err < 0) goto err_exit;
+ if (fprintf(__VA_ARGS__) < 0) goto err_exit;
#define EFFLUSH(x) \
- err = fflush(x); if (err != 0) goto err_exit;
+ if (fflush(x) != 0) goto err_exit;
static int
basl_fwrite_rsdp(FILE *fp)
{
- int err;
-
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve RSDP template\n");
EFPRINTF(fp, " */\n");
@@ -156,10 +152,6 @@ err_exit:
static int
basl_fwrite_rsdt(FILE *fp)
{
- int err;
-
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve RSDT template\n");
EFPRINTF(fp, " */\n");
@@ -196,10 +188,6 @@ err_exit:
static int
basl_fwrite_xsdt(FILE *fp)
{
- int err;
-
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve XSDT template\n");
EFPRINTF(fp, " */\n");
@@ -236,11 +224,8 @@ err_exit:
static int
basl_fwrite_madt(FILE *fp)
{
- int err;
int i;
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve MADT template\n");
EFPRINTF(fp, " */\n");
@@ -326,10 +311,6 @@ err_exit:
static int
basl_fwrite_fadt(FILE *fp)
{
- int err;
-
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve FADT template\n");
EFPRINTF(fp, " */\n");
@@ -547,10 +528,6 @@ err_exit:
static int
basl_fwrite_hpet(FILE *fp)
{
- int err;
-
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve HPET template\n");
EFPRINTF(fp, " */\n");
@@ -596,8 +573,6 @@ err_exit:
static int
basl_fwrite_mcfg(FILE *fp)
{
- int err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve MCFG template\n");
EFPRINTF(fp, " */\n");
@@ -629,10 +604,6 @@ err_exit:
static int
basl_fwrite_facs(FILE *fp)
{
- int err;
-
- err = 0;
-
EFPRINTF(fp, "/*\n");
EFPRINTF(fp, " * bhyve FACS template\n");
EFPRINTF(fp, " */\n");
@@ -666,7 +637,6 @@ void
dsdt_line(const char *fmt, ...)
{
va_list ap;
- int err;
if (dsdt_error != 0)
return;
@@ -675,8 +645,10 @@ dsdt_line(const char *fmt, ...)
if (dsdt_indent_level != 0)
EFPRINTF(dsdt_fp, "%*c", dsdt_indent_level * 2, ' ');
va_start(ap, fmt);
- if (vfprintf(dsdt_fp, fmt, ap) < 0)
+ if (vfprintf(dsdt_fp, fmt, ap) < 0) {
+ va_end(ap);
goto err_exit;
+ }
va_end(ap);
}
EFPRINTF(dsdt_fp, "\n");
@@ -735,9 +707,6 @@ dsdt_fixed_mem32(uint32_t base, uint32_t length)
static int
basl_fwrite_dsdt(FILE *fp)
{
- int err;
-
- err = 0;
dsdt_fp = fp;
dsdt_error = 0;
dsdt_indent_level = 0;
@@ -916,7 +885,7 @@ basl_make_templates(void)
int len;
err = 0;
-
+
/*
*
*/
Modified: stable/11/usr.sbin/bhyve/ahci.h
==============================================================================
--- stable/11/usr.sbin/bhyve/ahci.h Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/ahci.h Tue Jul 10 04:26:32 2018 (r336161)
@@ -33,292 +33,292 @@
#define _AHCI_H_
/* ATA register defines */
-#define ATA_DATA 0 /* (RW) data */
+#define ATA_DATA 0 /* (RW) data */
-#define ATA_FEATURE 1 /* (W) feature */
-#define ATA_F_DMA 0x01 /* enable DMA */
-#define ATA_F_OVL 0x02 /* enable overlap */
+#define ATA_FEATURE 1 /* (W) feature */
+#define ATA_F_DMA 0x01 /* enable DMA */
+#define ATA_F_OVL 0x02 /* enable overlap */
-#define ATA_COUNT 2 /* (W) sector count */
+#define ATA_COUNT 2 /* (W) sector count */
-#define ATA_SECTOR 3 /* (RW) sector # */
-#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
-#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
-#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
-#define ATA_D_LBA 0x40 /* use LBA addressing */
-#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
+#define ATA_SECTOR 3 /* (RW) sector # */
+#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
+#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
+#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
+#define ATA_D_LBA 0x40 /* use LBA addressing */
+#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
-#define ATA_COMMAND 7 /* (W) command */
+#define ATA_COMMAND 7 /* (W) command */
-#define ATA_ERROR 8 /* (R) error */
-#define ATA_E_ILI 0x01 /* illegal length */
-#define ATA_E_NM 0x02 /* no media */
-#define ATA_E_ABORT 0x04 /* command aborted */
-#define ATA_E_MCR 0x08 /* media change request */
-#define ATA_E_IDNF 0x10 /* ID not found */
-#define ATA_E_MC 0x20 /* media changed */
-#define ATA_E_UNC 0x40 /* uncorrectable data */
-#define ATA_E_ICRC 0x80 /* UDMA crc error */
-#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
+#define ATA_ERROR 8 /* (R) error */
+#define ATA_E_ILI 0x01 /* illegal length */
+#define ATA_E_NM 0x02 /* no media */
+#define ATA_E_ABORT 0x04 /* command aborted */
+#define ATA_E_MCR 0x08 /* media change request */
+#define ATA_E_IDNF 0x10 /* ID not found */
+#define ATA_E_MC 0x20 /* media changed */
+#define ATA_E_UNC 0x40 /* uncorrectable data */
+#define ATA_E_ICRC 0x80 /* UDMA crc error */
+#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
-#define ATA_IREASON 9 /* (R) interrupt reason */
-#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
-#define ATA_I_IN 0x02 /* read (1) | write (0) */
-#define ATA_I_RELEASE 0x04 /* released bus (1) */
-#define ATA_I_TAGMASK 0xf8 /* tag mask */
+#define ATA_IREASON 9 /* (R) interrupt reason */
+#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
+#define ATA_I_IN 0x02 /* read (1) | write (0) */
+#define ATA_I_RELEASE 0x04 /* released bus (1) */
+#define ATA_I_TAGMASK 0xf8 /* tag mask */
-#define ATA_STATUS 10 /* (R) status */
-#define ATA_ALTSTAT 11 /* (R) alternate status */
-#define ATA_S_ERROR 0x01 /* error */
-#define ATA_S_INDEX 0x02 /* index */
-#define ATA_S_CORR 0x04 /* data corrected */
-#define ATA_S_DRQ 0x08 /* data request */
-#define ATA_S_DSC 0x10 /* drive seek completed */
-#define ATA_S_SERVICE 0x10 /* drive needs service */
-#define ATA_S_DWF 0x20 /* drive write fault */
-#define ATA_S_DMA 0x20 /* DMA ready */
-#define ATA_S_READY 0x40 /* drive ready */
-#define ATA_S_BUSY 0x80 /* busy */
+#define ATA_STATUS 10 /* (R) status */
+#define ATA_ALTSTAT 11 /* (R) alternate status */
+#define ATA_S_ERROR 0x01 /* error */
+#define ATA_S_INDEX 0x02 /* index */
+#define ATA_S_CORR 0x04 /* data corrected */
+#define ATA_S_DRQ 0x08 /* data request */
+#define ATA_S_DSC 0x10 /* drive seek completed */
+#define ATA_S_SERVICE 0x10 /* drive needs service */
+#define ATA_S_DWF 0x20 /* drive write fault */
+#define ATA_S_DMA 0x20 /* DMA ready */
+#define ATA_S_READY 0x40 /* drive ready */
+#define ATA_S_BUSY 0x80 /* busy */
-#define ATA_CONTROL 12 /* (W) control */
-#define ATA_A_IDS 0x02 /* disable interrupts */
-#define ATA_A_RESET 0x04 /* RESET controller */
-#define ATA_A_4BIT 0x08 /* 4 head bits */
-#define ATA_A_HOB 0x80 /* High Order Byte enable */
+#define ATA_CONTROL 12 /* (W) control */
+#define ATA_A_IDS 0x02 /* disable interrupts */
+#define ATA_A_RESET 0x04 /* RESET controller */
+#define ATA_A_4BIT 0x08 /* 4 head bits */
+#define ATA_A_HOB 0x80 /* High Order Byte enable */
/* SATA register defines */
-#define ATA_SSTATUS 13
-#define ATA_SS_DET_MASK 0x0000000f
-#define ATA_SS_DET_NO_DEVICE 0x00000000
-#define ATA_SS_DET_DEV_PRESENT 0x00000001
-#define ATA_SS_DET_PHY_ONLINE 0x00000003
-#define ATA_SS_DET_PHY_OFFLINE 0x00000004
+#define ATA_SSTATUS 13
+#define ATA_SS_DET_MASK 0x0000000f
+#define ATA_SS_DET_NO_DEVICE 0x00000000
+#define ATA_SS_DET_DEV_PRESENT 0x00000001
+#define ATA_SS_DET_PHY_ONLINE 0x00000003
+#define ATA_SS_DET_PHY_OFFLINE 0x00000004
-#define ATA_SS_SPD_MASK 0x000000f0
-#define ATA_SS_SPD_NO_SPEED 0x00000000
-#define ATA_SS_SPD_GEN1 0x00000010
-#define ATA_SS_SPD_GEN2 0x00000020
-#define ATA_SS_SPD_GEN3 0x00000030
+#define ATA_SS_SPD_MASK 0x000000f0
+#define ATA_SS_SPD_NO_SPEED 0x00000000
+#define ATA_SS_SPD_GEN1 0x00000010
+#define ATA_SS_SPD_GEN2 0x00000020
+#define ATA_SS_SPD_GEN3 0x00000030
-#define ATA_SS_IPM_MASK 0x00000f00
-#define ATA_SS_IPM_NO_DEVICE 0x00000000
-#define ATA_SS_IPM_ACTIVE 0x00000100
-#define ATA_SS_IPM_PARTIAL 0x00000200
-#define ATA_SS_IPM_SLUMBER 0x00000600
-#define ATA_SS_IPM_DEVSLEEP 0x00000800
+#define ATA_SS_IPM_MASK 0x00000f00
+#define ATA_SS_IPM_NO_DEVICE 0x00000000
+#define ATA_SS_IPM_ACTIVE 0x00000100
+#define ATA_SS_IPM_PARTIAL 0x00000200
+#define ATA_SS_IPM_SLUMBER 0x00000600
+#define ATA_SS_IPM_DEVSLEEP 0x00000800
-#define ATA_SERROR 14
-#define ATA_SE_DATA_CORRECTED 0x00000001
-#define ATA_SE_COMM_CORRECTED 0x00000002
-#define ATA_SE_DATA_ERR 0x00000100
-#define ATA_SE_COMM_ERR 0x00000200
-#define ATA_SE_PROT_ERR 0x00000400
-#define ATA_SE_HOST_ERR 0x00000800
-#define ATA_SE_PHY_CHANGED 0x00010000
-#define ATA_SE_PHY_IERROR 0x00020000
-#define ATA_SE_COMM_WAKE 0x00040000
-#define ATA_SE_DECODE_ERR 0x00080000
-#define ATA_SE_PARITY_ERR 0x00100000
-#define ATA_SE_CRC_ERR 0x00200000
-#define ATA_SE_HANDSHAKE_ERR 0x00400000
-#define ATA_SE_LINKSEQ_ERR 0x00800000
-#define ATA_SE_TRANSPORT_ERR 0x01000000
-#define ATA_SE_UNKNOWN_FIS 0x02000000
-#define ATA_SE_EXCHANGED 0x04000000
+#define ATA_SERROR 14
+#define ATA_SE_DATA_CORRECTED 0x00000001
+#define ATA_SE_COMM_CORRECTED 0x00000002
+#define ATA_SE_DATA_ERR 0x00000100
+#define ATA_SE_COMM_ERR 0x00000200
+#define ATA_SE_PROT_ERR 0x00000400
+#define ATA_SE_HOST_ERR 0x00000800
+#define ATA_SE_PHY_CHANGED 0x00010000
+#define ATA_SE_PHY_IERROR 0x00020000
+#define ATA_SE_COMM_WAKE 0x00040000
+#define ATA_SE_DECODE_ERR 0x00080000
+#define ATA_SE_PARITY_ERR 0x00100000
+#define ATA_SE_CRC_ERR 0x00200000
+#define ATA_SE_HANDSHAKE_ERR 0x00400000
+#define ATA_SE_LINKSEQ_ERR 0x00800000
+#define ATA_SE_TRANSPORT_ERR 0x01000000
+#define ATA_SE_UNKNOWN_FIS 0x02000000
+#define ATA_SE_EXCHANGED 0x04000000
-#define ATA_SCONTROL 15
-#define ATA_SC_DET_MASK 0x0000000f
-#define ATA_SC_DET_IDLE 0x00000000
-#define ATA_SC_DET_RESET 0x00000001
-#define ATA_SC_DET_DISABLE 0x00000004
+#define ATA_SCONTROL 15
+#define ATA_SC_DET_MASK 0x0000000f
+#define ATA_SC_DET_IDLE 0x00000000
+#define ATA_SC_DET_RESET 0x00000001
+#define ATA_SC_DET_DISABLE 0x00000004
-#define ATA_SC_SPD_MASK 0x000000f0
-#define ATA_SC_SPD_NO_SPEED 0x00000000
-#define ATA_SC_SPD_SPEED_GEN1 0x00000010
-#define ATA_SC_SPD_SPEED_GEN2 0x00000020
-#define ATA_SC_SPD_SPEED_GEN3 0x00000030
+#define ATA_SC_SPD_MASK 0x000000f0
+#define ATA_SC_SPD_NO_SPEED 0x00000000
+#define ATA_SC_SPD_SPEED_GEN1 0x00000010
+#define ATA_SC_SPD_SPEED_GEN2 0x00000020
+#define ATA_SC_SPD_SPEED_GEN3 0x00000030
-#define ATA_SC_IPM_MASK 0x00000f00
-#define ATA_SC_IPM_NONE 0x00000000
-#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
-#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
-#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
+#define ATA_SC_IPM_MASK 0x00000f00
+#define ATA_SC_IPM_NONE 0x00000000
+#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
+#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
+#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
-#define ATA_SACTIVE 16
+#define ATA_SACTIVE 16
-#define AHCI_MAX_PORTS 32
-#define AHCI_MAX_SLOTS 32
-#define AHCI_MAX_IRQS 16
+#define AHCI_MAX_PORTS 32
+#define AHCI_MAX_SLOTS 32
+#define AHCI_MAX_IRQS 16
/* SATA AHCI v1.0 register defines */
-#define AHCI_CAP 0x00
-#define AHCI_CAP_NPMASK 0x0000001f
-#define AHCI_CAP_SXS 0x00000020
-#define AHCI_CAP_EMS 0x00000040
-#define AHCI_CAP_CCCS 0x00000080
-#define AHCI_CAP_NCS 0x00001F00
-#define AHCI_CAP_NCS_SHIFT 8
-#define AHCI_CAP_PSC 0x00002000
-#define AHCI_CAP_SSC 0x00004000
-#define AHCI_CAP_PMD 0x00008000
-#define AHCI_CAP_FBSS 0x00010000
-#define AHCI_CAP_SPM 0x00020000
-#define AHCI_CAP_SAM 0x00080000
-#define AHCI_CAP_ISS 0x00F00000
-#define AHCI_CAP_ISS_SHIFT 20
-#define AHCI_CAP_SCLO 0x01000000
-#define AHCI_CAP_SAL 0x02000000
-#define AHCI_CAP_SALP 0x04000000
-#define AHCI_CAP_SSS 0x08000000
-#define AHCI_CAP_SMPS 0x10000000
-#define AHCI_CAP_SSNTF 0x20000000
-#define AHCI_CAP_SNCQ 0x40000000
-#define AHCI_CAP_64BIT 0x80000000
+#define AHCI_CAP 0x00
+#define AHCI_CAP_NPMASK 0x0000001f
+#define AHCI_CAP_SXS 0x00000020
+#define AHCI_CAP_EMS 0x00000040
+#define AHCI_CAP_CCCS 0x00000080
+#define AHCI_CAP_NCS 0x00001F00
+#define AHCI_CAP_NCS_SHIFT 8
+#define AHCI_CAP_PSC 0x00002000
+#define AHCI_CAP_SSC 0x00004000
+#define AHCI_CAP_PMD 0x00008000
+#define AHCI_CAP_FBSS 0x00010000
+#define AHCI_CAP_SPM 0x00020000
+#define AHCI_CAP_SAM 0x00080000
+#define AHCI_CAP_ISS 0x00F00000
+#define AHCI_CAP_ISS_SHIFT 20
+#define AHCI_CAP_SCLO 0x01000000
+#define AHCI_CAP_SAL 0x02000000
+#define AHCI_CAP_SALP 0x04000000
+#define AHCI_CAP_SSS 0x08000000
+#define AHCI_CAP_SMPS 0x10000000
+#define AHCI_CAP_SSNTF 0x20000000
+#define AHCI_CAP_SNCQ 0x40000000
+#define AHCI_CAP_64BIT 0x80000000
-#define AHCI_GHC 0x04
-#define AHCI_GHC_AE 0x80000000
-#define AHCI_GHC_MRSM 0x00000004
-#define AHCI_GHC_IE 0x00000002
-#define AHCI_GHC_HR 0x00000001
+#define AHCI_GHC 0x04
+#define AHCI_GHC_AE 0x80000000
+#define AHCI_GHC_MRSM 0x00000004
+#define AHCI_GHC_IE 0x00000002
+#define AHCI_GHC_HR 0x00000001
-#define AHCI_IS 0x08
-#define AHCI_PI 0x0c
-#define AHCI_VS 0x10
+#define AHCI_IS 0x08
+#define AHCI_PI 0x0c
+#define AHCI_VS 0x10
-#define AHCI_CCCC 0x14
-#define AHCI_CCCC_TV_MASK 0xffff0000
-#define AHCI_CCCC_TV_SHIFT 16
-#define AHCI_CCCC_CC_MASK 0x0000ff00
-#define AHCI_CCCC_CC_SHIFT 8
-#define AHCI_CCCC_INT_MASK 0x000000f8
-#define AHCI_CCCC_INT_SHIFT 3
-#define AHCI_CCCC_EN 0x00000001
-#define AHCI_CCCP 0x18
+#define AHCI_CCCC 0x14
+#define AHCI_CCCC_TV_MASK 0xffff0000
+#define AHCI_CCCC_TV_SHIFT 16
+#define AHCI_CCCC_CC_MASK 0x0000ff00
+#define AHCI_CCCC_CC_SHIFT 8
+#define AHCI_CCCC_INT_MASK 0x000000f8
+#define AHCI_CCCC_INT_SHIFT 3
+#define AHCI_CCCC_EN 0x00000001
+#define AHCI_CCCP 0x18
-#define AHCI_EM_LOC 0x1C
-#define AHCI_EM_CTL 0x20
-#define AHCI_EM_MR 0x00000001
-#define AHCI_EM_TM 0x00000100
-#define AHCI_EM_RST 0x00000200
-#define AHCI_EM_LED 0x00010000
-#define AHCI_EM_SAFTE 0x00020000
-#define AHCI_EM_SES2 0x00040000
-#define AHCI_EM_SGPIO 0x00080000
-#define AHCI_EM_SMB 0x01000000
-#define AHCI_EM_XMT 0x02000000
-#define AHCI_EM_ALHD 0x04000000
-#define AHCI_EM_PM 0x08000000
+#define AHCI_EM_LOC 0x1C
+#define AHCI_EM_CTL 0x20
+#define AHCI_EM_MR 0x00000001
+#define AHCI_EM_TM 0x00000100
+#define AHCI_EM_RST 0x00000200
+#define AHCI_EM_LED 0x00010000
+#define AHCI_EM_SAFTE 0x00020000
+#define AHCI_EM_SES2 0x00040000
+#define AHCI_EM_SGPIO 0x00080000
+#define AHCI_EM_SMB 0x01000000
+#define AHCI_EM_XMT 0x02000000
+#define AHCI_EM_ALHD 0x04000000
+#define AHCI_EM_PM 0x08000000
-#define AHCI_CAP2 0x24
-#define AHCI_CAP2_BOH 0x00000001
-#define AHCI_CAP2_NVMP 0x00000002
-#define AHCI_CAP2_APST 0x00000004
-#define AHCI_CAP2_SDS 0x00000008
-#define AHCI_CAP2_SADM 0x00000010
-#define AHCI_CAP2_DESO 0x00000020
+#define AHCI_CAP2 0x24
+#define AHCI_CAP2_BOH 0x00000001
+#define AHCI_CAP2_NVMP 0x00000002
+#define AHCI_CAP2_APST 0x00000004
+#define AHCI_CAP2_SDS 0x00000008
+#define AHCI_CAP2_SADM 0x00000010
+#define AHCI_CAP2_DESO 0x00000020
-#define AHCI_OFFSET 0x100
-#define AHCI_STEP 0x80
+#define AHCI_OFFSET 0x100
+#define AHCI_STEP 0x80
-#define AHCI_P_CLB 0x00
-#define AHCI_P_CLBU 0x04
-#define AHCI_P_FB 0x08
-#define AHCI_P_FBU 0x0c
-#define AHCI_P_IS 0x10
-#define AHCI_P_IE 0x14
-#define AHCI_P_IX_DHR 0x00000001
-#define AHCI_P_IX_PS 0x00000002
-#define AHCI_P_IX_DS 0x00000004
-#define AHCI_P_IX_SDB 0x00000008
-#define AHCI_P_IX_UF 0x00000010
-#define AHCI_P_IX_DP 0x00000020
-#define AHCI_P_IX_PC 0x00000040
-#define AHCI_P_IX_MP 0x00000080
+#define AHCI_P_CLB 0x00
+#define AHCI_P_CLBU 0x04
+#define AHCI_P_FB 0x08
+#define AHCI_P_FBU 0x0c
+#define AHCI_P_IS 0x10
+#define AHCI_P_IE 0x14
+#define AHCI_P_IX_DHR 0x00000001
+#define AHCI_P_IX_PS 0x00000002
+#define AHCI_P_IX_DS 0x00000004
+#define AHCI_P_IX_SDB 0x00000008
+#define AHCI_P_IX_UF 0x00000010
+#define AHCI_P_IX_DP 0x00000020
+#define AHCI_P_IX_PC 0x00000040
+#define AHCI_P_IX_MP 0x00000080
-#define AHCI_P_IX_PRC 0x00400000
-#define AHCI_P_IX_IPM 0x00800000
-#define AHCI_P_IX_OF 0x01000000
-#define AHCI_P_IX_INF 0x04000000
-#define AHCI_P_IX_IF 0x08000000
-#define AHCI_P_IX_HBD 0x10000000
-#define AHCI_P_IX_HBF 0x20000000
-#define AHCI_P_IX_TFE 0x40000000
-#define AHCI_P_IX_CPD 0x80000000
+#define AHCI_P_IX_PRC 0x00400000
+#define AHCI_P_IX_IPM 0x00800000
+#define AHCI_P_IX_OF 0x01000000
+#define AHCI_P_IX_INF 0x04000000
+#define AHCI_P_IX_IF 0x08000000
+#define AHCI_P_IX_HBD 0x10000000
+#define AHCI_P_IX_HBF 0x20000000
+#define AHCI_P_IX_TFE 0x40000000
+#define AHCI_P_IX_CPD 0x80000000
-#define AHCI_P_CMD 0x18
-#define AHCI_P_CMD_ST 0x00000001
-#define AHCI_P_CMD_SUD 0x00000002
-#define AHCI_P_CMD_POD 0x00000004
-#define AHCI_P_CMD_CLO 0x00000008
-#define AHCI_P_CMD_FRE 0x00000010
-#define AHCI_P_CMD_CCS_MASK 0x00001f00
-#define AHCI_P_CMD_CCS_SHIFT 8
-#define AHCI_P_CMD_ISS 0x00002000
-#define AHCI_P_CMD_FR 0x00004000
-#define AHCI_P_CMD_CR 0x00008000
-#define AHCI_P_CMD_CPS 0x00010000
-#define AHCI_P_CMD_PMA 0x00020000
-#define AHCI_P_CMD_HPCP 0x00040000
-#define AHCI_P_CMD_MPSP 0x00080000
-#define AHCI_P_CMD_CPD 0x00100000
-#define AHCI_P_CMD_ESP 0x00200000
-#define AHCI_P_CMD_FBSCP 0x00400000
-#define AHCI_P_CMD_APSTE 0x00800000
-#define AHCI_P_CMD_ATAPI 0x01000000
-#define AHCI_P_CMD_DLAE 0x02000000
-#define AHCI_P_CMD_ALPE 0x04000000
-#define AHCI_P_CMD_ASP 0x08000000
-#define AHCI_P_CMD_ICC_MASK 0xf0000000
-#define AHCI_P_CMD_NOOP 0x00000000
-#define AHCI_P_CMD_ACTIVE 0x10000000
-#define AHCI_P_CMD_PARTIAL 0x20000000
-#define AHCI_P_CMD_SLUMBER 0x60000000
-#define AHCI_P_CMD_DEVSLEEP 0x80000000
+#define AHCI_P_CMD 0x18
+#define AHCI_P_CMD_ST 0x00000001
+#define AHCI_P_CMD_SUD 0x00000002
+#define AHCI_P_CMD_POD 0x00000004
+#define AHCI_P_CMD_CLO 0x00000008
+#define AHCI_P_CMD_FRE 0x00000010
+#define AHCI_P_CMD_CCS_MASK 0x00001f00
+#define AHCI_P_CMD_CCS_SHIFT 8
+#define AHCI_P_CMD_ISS 0x00002000
+#define AHCI_P_CMD_FR 0x00004000
+#define AHCI_P_CMD_CR 0x00008000
+#define AHCI_P_CMD_CPS 0x00010000
+#define AHCI_P_CMD_PMA 0x00020000
+#define AHCI_P_CMD_HPCP 0x00040000
+#define AHCI_P_CMD_MPSP 0x00080000
+#define AHCI_P_CMD_CPD 0x00100000
+#define AHCI_P_CMD_ESP 0x00200000
+#define AHCI_P_CMD_FBSCP 0x00400000
+#define AHCI_P_CMD_APSTE 0x00800000
+#define AHCI_P_CMD_ATAPI 0x01000000
+#define AHCI_P_CMD_DLAE 0x02000000
+#define AHCI_P_CMD_ALPE 0x04000000
+#define AHCI_P_CMD_ASP 0x08000000
+#define AHCI_P_CMD_ICC_MASK 0xf0000000
+#define AHCI_P_CMD_NOOP 0x00000000
+#define AHCI_P_CMD_ACTIVE 0x10000000
+#define AHCI_P_CMD_PARTIAL 0x20000000
+#define AHCI_P_CMD_SLUMBER 0x60000000
+#define AHCI_P_CMD_DEVSLEEP 0x80000000
-#define AHCI_P_TFD 0x20
-#define AHCI_P_SIG 0x24
-#define AHCI_P_SSTS 0x28
-#define AHCI_P_SCTL 0x2c
-#define AHCI_P_SERR 0x30
-#define AHCI_P_SACT 0x34
-#define AHCI_P_CI 0x38
-#define AHCI_P_SNTF 0x3C
-#define AHCI_P_FBS 0x40
-#define AHCI_P_FBS_EN 0x00000001
-#define AHCI_P_FBS_DEC 0x00000002
-#define AHCI_P_FBS_SDE 0x00000004
-#define AHCI_P_FBS_DEV 0x00000f00
-#define AHCI_P_FBS_DEV_SHIFT 8
-#define AHCI_P_FBS_ADO 0x0000f000
-#define AHCI_P_FBS_ADO_SHIFT 12
-#define AHCI_P_FBS_DWE 0x000f0000
-#define AHCI_P_FBS_DWE_SHIFT 16
-#define AHCI_P_DEVSLP 0x44
-#define AHCI_P_DEVSLP_ADSE 0x00000001
-#define AHCI_P_DEVSLP_DSP 0x00000002
-#define AHCI_P_DEVSLP_DETO 0x000003fc
-#define AHCI_P_DEVSLP_DETO_SHIFT 2
-#define AHCI_P_DEVSLP_MDAT 0x00007c00
-#define AHCI_P_DEVSLP_MDAT_SHIFT 10
-#define AHCI_P_DEVSLP_DITO 0x01ff8000
-#define AHCI_P_DEVSLP_DITO_SHIFT 15
-#define AHCI_P_DEVSLP_DM 0x0e000000
-#define AHCI_P_DEVSLP_DM_SHIFT 25
+#define AHCI_P_TFD 0x20
+#define AHCI_P_SIG 0x24
+#define AHCI_P_SSTS 0x28
+#define AHCI_P_SCTL 0x2c
+#define AHCI_P_SERR 0x30
+#define AHCI_P_SACT 0x34
+#define AHCI_P_CI 0x38
+#define AHCI_P_SNTF 0x3C
+#define AHCI_P_FBS 0x40
+#define AHCI_P_FBS_EN 0x00000001
+#define AHCI_P_FBS_DEC 0x00000002
+#define AHCI_P_FBS_SDE 0x00000004
+#define AHCI_P_FBS_DEV 0x00000f00
+#define AHCI_P_FBS_DEV_SHIFT 8
+#define AHCI_P_FBS_ADO 0x0000f000
+#define AHCI_P_FBS_ADO_SHIFT 12
+#define AHCI_P_FBS_DWE 0x000f0000
+#define AHCI_P_FBS_DWE_SHIFT 16
+#define AHCI_P_DEVSLP 0x44
+#define AHCI_P_DEVSLP_ADSE 0x00000001
+#define AHCI_P_DEVSLP_DSP 0x00000002
+#define AHCI_P_DEVSLP_DETO 0x000003fc
+#define AHCI_P_DEVSLP_DETO_SHIFT 2
+#define AHCI_P_DEVSLP_MDAT 0x00007c00
+#define AHCI_P_DEVSLP_MDAT_SHIFT 10
+#define AHCI_P_DEVSLP_DITO 0x01ff8000
+#define AHCI_P_DEVSLP_DITO_SHIFT 15
+#define AHCI_P_DEVSLP_DM 0x0e000000
+#define AHCI_P_DEVSLP_DM_SHIFT 25
/* Just to be sure, if building as module. */
#if MAXPHYS < 512 * 1024
#undef MAXPHYS
-#define MAXPHYS 512 * 1024
+#define MAXPHYS 512 * 1024
#endif
/* Pessimistic prognosis on number of required S/G entries */
-#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
+#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
/* Command list. 32 commands. First, 1Kbyte aligned. */
-#define AHCI_CL_OFFSET 0
-#define AHCI_CL_SIZE 32
+#define AHCI_CL_OFFSET 0
+#define AHCI_CL_SIZE 32
/* Command tables. Up to 32 commands, Each, 128byte aligned. */
-#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
-#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
+#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
+#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
/* Total main work area. */
-#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
+#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
#endif /* _AHCI_H_ */
Modified: stable/11/usr.sbin/bhyve/bhyverun.c
==============================================================================
--- stable/11/usr.sbin/bhyve/bhyverun.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/bhyverun.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -115,14 +115,14 @@ static void vm_loop(struct vmctx *ctx, int vcpu, uint6
static struct vm_exit vmexit[VM_MAXCPU];
struct bhyvestats {
- uint64_t vmexit_bogus;
+ uint64_t vmexit_bogus;
uint64_t vmexit_reqidle;
- uint64_t vmexit_hlt;
- uint64_t vmexit_pause;
- uint64_t vmexit_mtrap;
- uint64_t vmexit_inst_emul;
- uint64_t cpu_switch_rotate;
- uint64_t cpu_switch_direct;
+ uint64_t vmexit_hlt;
+ uint64_t vmexit_pause;
+ uint64_t vmexit_mtrap;
+ uint64_t vmexit_inst_emul;
+ uint64_t cpu_switch_rotate;
+ uint64_t cpu_switch_direct;
} stats;
struct mt_vmm_info {
@@ -354,7 +354,7 @@ vmexit_handle_notify(struct vmctx *ctx, struct vm_exit
* put guest-driven debug here
*/
#endif
- return (VMEXIT_CONTINUE);
+ return (VMEXIT_CONTINUE);
}
static int
Modified: stable/11/usr.sbin/bhyve/block_if.c
==============================================================================
--- stable/11/usr.sbin/bhyve/block_if.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/block_if.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -101,8 +101,8 @@ struct blockif_ctxt {
int bc_psectoff;
int bc_closing;
pthread_t bc_btid[BLOCKIF_NUMTHR];
- pthread_mutex_t bc_mtx;
- pthread_cond_t bc_cond;
+ pthread_mutex_t bc_mtx;
+ pthread_cond_t bc_cond;
/* Request elements and free/pending/busy queues */
TAILQ_HEAD(, blockif_elem) bc_freeq;
Modified: stable/11/usr.sbin/bhyve/bootrom.h
==============================================================================
--- stable/11/usr.sbin/bhyve/bootrom.h Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/bootrom.h Tue Jul 10 04:26:32 2018 (r336161)
@@ -33,6 +33,6 @@
struct vmctx;
-int bootrom_init(struct vmctx *ctx, const char *romfile);
+int bootrom_init(struct vmctx *ctx, const char *romfile);
#endif
Modified: stable/11/usr.sbin/bhyve/console.h
==============================================================================
--- stable/11/usr.sbin/bhyve/console.h Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/console.h Tue Jul 10 04:26:32 2018 (r336161)
@@ -35,19 +35,19 @@ typedef void (*fb_render_func_t)(struct bhyvegc *gc, v
typedef void (*kbd_event_func_t)(int down, uint32_t keysym, void *arg);
typedef void (*ptr_event_func_t)(uint8_t mask, int x, int y, void *arg);
-void console_init(int w, int h, void *fbaddr);
+void console_init(int w, int h, void *fbaddr);
-void console_set_fbaddr(void *fbaddr);
+void console_set_fbaddr(void *fbaddr);
struct bhyvegc_image *console_get_image(void);
-void console_fb_register(fb_render_func_t render_cb, void *arg);
-void console_refresh(void);
+void console_fb_register(fb_render_func_t render_cb, void *arg);
+void console_refresh(void);
-void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri);
-void console_key_event(int down, uint32_t keysym);
+void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri);
+void console_key_event(int down, uint32_t keysym);
-void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri);
-void console_ptr_event(uint8_t button, int x, int y);
+void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri);
+void console_ptr_event(uint8_t button, int x, int y);
#endif /* _CONSOLE_H_ */
Modified: stable/11/usr.sbin/bhyve/consport.c
==============================================================================
--- stable/11/usr.sbin/bhyve/consport.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/consport.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -74,14 +74,14 @@ ttyopen(void)
static bool
tty_char_available(void)
{
- fd_set rfds;
- struct timeval tv;
+ fd_set rfds;
+ struct timeval tv;
- FD_ZERO(&rfds);
- FD_SET(STDIN_FILENO, &rfds);
- tv.tv_sec = 0;
- tv.tv_usec = 0;
- if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0) {
+ FD_ZERO(&rfds);
+ FD_SET(STDIN_FILENO, &rfds);
+ tv.tv_sec = 0;
+ tv.tv_usec = 0;
+ if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0) {
return (true);
} else {
return (false);
Modified: stable/11/usr.sbin/bhyve/inout.c
==============================================================================
--- stable/11/usr.sbin/bhyve/inout.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/inout.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -68,21 +68,21 @@ static int
default_inout(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
uint32_t *eax, void *arg)
{
- if (in) {
- switch (bytes) {
- case 4:
- *eax = 0xffffffff;
- break;
- case 2:
- *eax = 0xffff;
- break;
- case 1:
- *eax = 0xff;
- break;
- }
- }
-
- return (0);
+ if (in) {
+ switch (bytes) {
+ case 4:
+ *eax = 0xffffffff;
+ break;
+ case 2:
+ *eax = 0xffff;
+ break;
+ case 1:
+ *eax = 0xff;
+ break;
+ }
+ }
+
+ return (0);
}
static void
Modified: stable/11/usr.sbin/bhyve/mem.h
==============================================================================
--- stable/11/usr.sbin/bhyve/mem.h Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/mem.h Tue Jul 10 04:26:32 2018 (r336161)
@@ -55,7 +55,7 @@ struct mem_range {
void init_mem(void);
int emulate_mem(struct vmctx *, int vcpu, uint64_t paddr, struct vie *vie,
struct vm_guest_paging *paging);
-
+
int register_mem(struct mem_range *memp);
int register_mem_fallback(struct mem_range *memp);
int unregister_mem(struct mem_range *memp);
Modified: stable/11/usr.sbin/bhyve/mevent.c
==============================================================================
--- stable/11/usr.sbin/bhyve/mevent.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/mevent.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -71,7 +71,7 @@ static int mevent_timid = 43;
static int mevent_pipefd[2];
static pthread_mutex_t mevent_lmutex = PTHREAD_MUTEX_INITIALIZER;
-struct mevent {
+struct mevent {
void (*me_func)(int, enum ev_type, void *);
#define me_msecs me_fd
int me_fd;
@@ -81,7 +81,7 @@ struct mevent {
int me_cq;
int me_state;
int me_closefd;
- LIST_ENTRY(mevent) me_list;
+ LIST_ENTRY(mevent) me_list;
};
static LIST_HEAD(listhead, mevent) global_head, change_head;
Modified: stable/11/usr.sbin/bhyve/mevent_test.c
==============================================================================
--- stable/11/usr.sbin/bhyve/mevent_test.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/mevent_test.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -199,25 +199,25 @@ acceptor(void *param)
int s;
static int first;
- if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
- perror("socket");
- exit(1);
- }
+ if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
+ perror("socket");
+ exit(1);
+ }
- sin.sin_len = sizeof(sin);
- sin.sin_family = AF_INET;
- sin.sin_addr.s_addr = htonl(INADDR_ANY);
- sin.sin_port = htons(TEST_PORT);
+ sin.sin_len = sizeof(sin);
+ sin.sin_family = AF_INET;
+ sin.sin_addr.s_addr = htonl(INADDR_ANY);
+ sin.sin_port = htons(TEST_PORT);
- if (bind(s, (struct sockaddr *)&sin, sizeof(sin)) < 0) {
- perror("bind");
- exit(1);
- }
+ if (bind(s, (struct sockaddr *)&sin, sizeof(sin)) < 0) {
+ perror("bind");
+ exit(1);
+ }
- if (listen(s, 1) < 0) {
- perror("listen");
- exit(1);
- }
+ if (listen(s, 1) < 0) {
+ perror("listen");
+ exit(1);
+ }
(void) mevent_add(s, EVF_READ, acceptor_callback, NULL);
Modified: stable/11/usr.sbin/bhyve/pci_e82545.c
==============================================================================
--- stable/11/usr.sbin/bhyve/pci_e82545.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/pci_e82545.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -342,8 +342,8 @@ struct e82545_softc {
#define E82545_NVM_MODE_OPADDR 0x0
#define E82545_NVM_MODE_DATAIN 0x1
#define E82545_NVM_MODE_DATAOUT 0x2
- /* EEPROM data */
- uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
+ /* EEPROM data */
+ uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
};
static void e82545_reset(struct e82545_softc *sc, int dev);
@@ -1470,7 +1470,7 @@ e82545_rx_disable(struct e82545_softc *sc)
static void
e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
{
- struct eth_uni *eu;
+ struct eth_uni *eu;
int idx;
idx = reg >> 1;
@@ -1496,7 +1496,7 @@ e82545_write_ra(struct e82545_softc *sc, int reg, uint
static uint32_t
e82545_read_ra(struct e82545_softc *sc, int reg)
{
- struct eth_uni *eu;
+ struct eth_uni *eu;
uint32_t retval;
int idx;
@@ -1740,12 +1740,12 @@ e82545_read_register(struct e82545_softc *sc, uint32_t
{
uint32_t retval;
int ridx;
-
+
if (offset & 0x3) {
DPRINTF("Unaligned register read offset:0x%x\r\n", offset);
return 0;
}
-
+
DPRINTF("Register read: 0x%x\r\n", offset);
switch (offset) {
Modified: stable/11/usr.sbin/bhyve/pci_emul.c
==============================================================================
--- stable/11/usr.sbin/bhyve/pci_emul.c Tue Jul 10 03:49:48 2018 (r336160)
+++ stable/11/usr.sbin/bhyve/pci_emul.c Tue Jul 10 04:26:32 2018 (r336161)
@@ -863,7 +863,7 @@ msixcap_cfgwrite(struct pci_devinst *pi, int capoff, i
{
uint16_t msgctrl, rwmask;
int off;
-
+
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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