svn commit: r266374 - in stable/10/sys/arm: arm include

[Ian Lepore]

Author: ian
Date: Sat May 17 23:03:04 2014
New Revision: 266374
URL: http://svnweb.freebsd.org/changeset/base/266374

Log:
  MFC 265023, 265024, 265036:
  
    There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
    map them both to the same interrupt number like other arches do.
  
    Flush and invalidate caches on each CPU as part of handling IPI_STOP.
  
    Don't use multiprocessing-extensions instruction on processors that don't
    support SMP.

Modified:
  stable/10/sys/arm/arm/cpufunc_asm_armv7.S
  stable/10/sys/arm/arm/minidump_machdep.c
  stable/10/sys/arm/arm/mp_machdep.c
  stable/10/sys/arm/include/smp.h
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- stable/10/sys/arm/arm/cpufunc_asm_armv7.S	Sat May 17 22:50:16 2014	(r266373)
+++ stable/10/sys/arm/arm/cpufunc_asm_armv7.S	Sat May 17 23:03:04 2014	(r266374)
@@ -251,7 +251,11 @@ ENTRY(armv7_idcache_wbinv_range)
 END(armv7_idcache_wbinv_range)
 
 ENTRY_NP(armv7_icache_sync_all)
+#ifdef SMP
 	mcr	p15, 0, r0, c7, c1, 0	/* Invalidate all I cache to PoU Inner Shareable */
+#else
+	mcr	p15, 0, r0, c7, c5, 0	/* Invalidate all I cache to PoU (ICIALLU) */
+#endif
 	isb				/* instruction synchronization barrier */
 	dsb				/* data synchronization barrier */
 	RET

Modified: stable/10/sys/arm/arm/minidump_machdep.c
==============================================================================
--- stable/10/sys/arm/arm/minidump_machdep.c	Sat May 17 22:50:16 2014	(r266373)
+++ stable/10/sys/arm/arm/minidump_machdep.c	Sat May 17 23:03:04 2014	(r266374)
@@ -210,7 +210,15 @@ minidumpsys(struct dumperinfo *di)
 	int i, k, bit, error;
 	char *addr;
 
-	/* Flush cache */
+	/*
+	 * Flush caches.  Note that in the SMP case this operates only on the
+	 * current CPU's L1 cache.  Before we reach this point, code in either
+	 * the system shutdown or kernel debugger has called stop_cpus() to stop
+	 * all cores other than this one.  Part of the ARM handling of
+	 * stop_cpus() is to call wbinv_all() on that core's local L1 cache.  So
+	 * by time we get to here, all that remains is to flush the L1 for the
+	 * current CPU, then the L2.
+	 */
 	cpu_idcache_wbinv_all();
 	cpu_l2cache_wbinv_all();
 

Modified: stable/10/sys/arm/arm/mp_machdep.c
==============================================================================
--- stable/10/sys/arm/arm/mp_machdep.c	Sat May 17 22:50:16 2014	(r266373)
+++ stable/10/sys/arm/arm/mp_machdep.c	Sat May 17 23:03:04 2014	(r266374)
@@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$");
 #include <vm/pmap.h>
 
 #include <machine/cpu.h>
+#include <machine/cpufunc.h>
 #include <machine/smp.h>
 #include <machine/pcb.h>
 #include <machine/pte.h>
@@ -278,7 +279,6 @@ ipi_handler(void *arg)
 			break;
 
 		case IPI_STOP:
-		case IPI_STOP_HARD:
 			/*
 			 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
 			 * necessary to add it in the switch.
@@ -287,6 +287,19 @@ ipi_handler(void *arg)
 
 			savectx(&stoppcbs[cpu]);
 
+			/*
+			 * CPUs are stopped when entering the debugger and at
+			 * system shutdown, both events which can precede a
+			 * panic dump.  For the dump to be correct, all caches
+			 * must be flushed and invalidated, but on ARM there's
+			 * no way to broadcast a wbinv_all to other cores.
+			 * Instead, we have each core do the local wbinv_all as
+			 * part of stopping the core.  The core requesting the
+			 * stop will do the l2 cache flush after all other cores
+			 * have done their l1 flushes and stopped.
+			 */
+			cpu_idcache_wbinv_all();
+
 			/* Indicate we are stopped */
 			CPU_SET_ATOMIC(cpu, &stopped_cpus);
 

Modified: stable/10/sys/arm/include/smp.h
==============================================================================
--- stable/10/sys/arm/include/smp.h	Sat May 17 22:50:16 2014	(r266373)
+++ stable/10/sys/arm/include/smp.h	Sat May 17 23:03:04 2014	(r266374)
@@ -10,7 +10,7 @@
 #define IPI_PREEMPT	2
 #define IPI_RENDEZVOUS	3
 #define IPI_STOP	4
-#define IPI_STOP_HARD	5
+#define IPI_STOP_HARD	4
 #define IPI_HARDCLOCK	6
 #define IPI_TLB		7