svn commit: r190067 - in stable/7/sys: . contrib/pf dev/ath/ath_hal dev/cxgb sparc64/sparc64

[Marius Strobl]

Author: marius
Date: Thu Mar 19 15:32:16 2009
New Revision: 190067
URL: http://svn.freebsd.org/changeset/base/190067

Log:
  MFC: r185007
  
  Use the spitfire VIS block copy/zero functions also with cheetah-
  class CPUs. In theory one could also use versions additionally
  taking advantage of the prefetch cache with cheetah-class CPUs,
  in my worldstone runs these either didn't provide extra speedup
  (USIII+) in comparison to the existing spitfire versions or were
  even slightly slower (USIIIi) though, so they aren't committed
  for now.
  The basic problem leading to the VIS-based copy/zero functions
  being initially disabled for cheetah-class CPUs was solved by
  letting cheetah_init() clear DCR_IFPOE.

Modified:
  stable/7/sys/   (props changed)
  stable/7/sys/contrib/pf/   (props changed)
  stable/7/sys/dev/ath/ath_hal/   (props changed)
  stable/7/sys/dev/cxgb/   (props changed)
  stable/7/sys/sparc64/sparc64/machdep.c

Modified: stable/7/sys/sparc64/sparc64/machdep.c
==============================================================================
--- stable/7/sys/sparc64/sparc64/machdep.c	Thu Mar 19 15:30:45 2009	(r190066)
+++ stable/7/sys/sparc64/sparc64/machdep.c	Thu Mar 19 15:32:16 2009	(r190067)
@@ -387,6 +387,12 @@ sparc64_init(caddr_t mdp, u_long o1, u_l
 		case CPU_IMPL_ULTRASPARCII:
 		case CPU_IMPL_ULTRASPARCIIi:
 		case CPU_IMPL_ULTRASPARCIIe:
+		case CPU_IMPL_ULTRASPARCIII:	/* NB: we've disabled P$. */
+		case CPU_IMPL_ULTRASPARCIIIp:
+		case CPU_IMPL_ULTRASPARCIIIi:
+		case CPU_IMPL_ULTRASPARCIV:
+		case CPU_IMPL_ULTRASPARCIVp:
+		case CPU_IMPL_ULTRASPARCIIIip:
 			cpu_block_copy = spitfire_block_copy;
 			cpu_block_zero = spitfire_block_zero;
 			break;
@@ -773,7 +779,7 @@ sparc64_shutdown_final(void *dummy, int 
 	/* Turn the power off? */
 	if ((howto & RB_POWEROFF) != 0)
 		cpu_shutdown(&args);
-	/* In case of halt, return to the firmware */
+	/* In case of halt, return to the firmware. */
 	if ((howto & RB_HALT) != 0)
 		cpu_halt();
 }