svn commit: r331962 - in projects/krb5: include lib/libc/stdio share/man/man8 sys/arm/conf sys/arm/include sys/arm/mv sys/arm/mv/armada sys/arm/mv/armada38x sys/arm/mv/armadaxp sys/cddl/contrib/ope...
Cy Schubert
cy at FreeBSD.org
Tue Apr 3 22:50:00 UTC 2018
Author: cy
Date: Tue Apr 3 22:49:58 2018
New Revision: 331962
URL: https://svnweb.freebsd.org/changeset/base/331962
Log:
MFH to r331961.
Added:
projects/krb5/sys/arm/mv/files.arm7
- copied unchanged from r331961, head/sys/arm/mv/files.arm7
projects/krb5/usr.bin/etdump/
- copied from r331961, head/usr.bin/etdump/
Modified:
projects/krb5/include/stdio.h
projects/krb5/lib/libc/stdio/Symbol.map
projects/krb5/share/man/man8/rc.subr.8
projects/krb5/sys/arm/conf/ARMADAXP
projects/krb5/sys/arm/include/intr.h
projects/krb5/sys/arm/mv/armada/wdt.c
projects/krb5/sys/arm/mv/armada38x/armada38x.c
projects/krb5/sys/arm/mv/armada38x/std.armada38x
projects/krb5/sys/arm/mv/armadaxp/armadaxp.c
projects/krb5/sys/arm/mv/mpic.c
projects/krb5/sys/arm/mv/mv_common.c
projects/krb5/sys/arm/mv/mv_machdep.c
projects/krb5/sys/arm/mv/mv_pci.c
projects/krb5/sys/arm/mv/mvreg.h
projects/krb5/sys/arm/mv/mvvar.h
projects/krb5/sys/arm/mv/mvwin.h
projects/krb5/sys/arm/mv/std-pj4b.mv
projects/krb5/sys/arm/mv/timer.c
projects/krb5/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_removal.c
projects/krb5/sys/dts/arm/db78460.dts
projects/krb5/sys/opencrypto/cryptosoft.c
projects/krb5/usr.bin/Makefile
Directory Properties:
projects/krb5/ (props changed)
projects/krb5/sys/cddl/contrib/opensolaris/ (props changed)
Modified: projects/krb5/include/stdio.h
==============================================================================
--- projects/krb5/include/stdio.h Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/include/stdio.h Tue Apr 3 22:49:58 2018 (r331962)
@@ -270,7 +270,7 @@ size_t fwrite(const void * __restrict, size_t, size_t
int getc(FILE *);
int getchar(void);
char *gets(char *);
-#if defined(__EXT1_VISIBLE) && __EXT1_VISIBLE == 1
+#if __EXT1_VISIBLE
char *gets_s(char *, rsize_t);
#endif
void perror(const char *);
Modified: projects/krb5/lib/libc/stdio/Symbol.map
==============================================================================
--- projects/krb5/lib/libc/stdio/Symbol.map Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/lib/libc/stdio/Symbol.map Tue Apr 3 22:49:58 2018 (r331962)
@@ -160,12 +160,15 @@ FBSD_1.3 {
open_wmemstream;
mkostemp;
mkostemps;
- gets_s;
};
FBSD_1.4 {
fdclose;
fopencookie;
+};
+
+FBSD_1.5 {
+ gets_s;
};
FBSDprivate_1.0 {
Modified: projects/krb5/share/man/man8/rc.subr.8
==============================================================================
--- projects/krb5/share/man/man8/rc.subr.8 Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/share/man/man8/rc.subr.8 Tue Apr 3 22:49:58 2018 (r331962)
@@ -29,7 +29,7 @@
.\"
.\" $FreeBSD$
.\"
-.Dd September 18, 2016
+.Dd April 3, 2018
.Dt RC.SUBR 8
.Os
.Sh NAME
@@ -584,21 +584,27 @@ Only supported after
.Pa /usr
is mounted.
.It Va ${name}_limits
-.Xr limits 1
-to apply to
+Resource limits to apply to
.Va command .
This will be passed as arguments to the
.Xr limits 1
utility.
+By default, the resource limits are based on the login class defined in
+.Va ${name}_login_class .
+.It Va ${name}_login_class
+Login class to use with
+.Va ${name}_limits .
+Defaults to
+.Dq Li daemon .
.It Va ${name}_oomprotect
.Xr protect 1
.Va command
from being killed when swap space is exhausted.
If
-.Em YES
+.Dq Li YES
is used, no child processes are protected.
If
-.Em ALL ,
+.Dq Li ALL ,
protect all child processes.
.It Va ${name}_program
Full path to the command.
Modified: projects/krb5/sys/arm/conf/ARMADAXP
==============================================================================
--- projects/krb5/sys/arm/conf/ARMADAXP Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/conf/ARMADAXP Tue Apr 3 22:49:58 2018 (r331962)
@@ -88,3 +88,5 @@ device pci
options FDT # Configure using FDT/DTB data
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=db78460.dts
+
+options INTRNG
Modified: projects/krb5/sys/arm/include/intr.h
==============================================================================
--- projects/krb5/sys/arm/include/intr.h Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/include/intr.h Tue Apr 3 22:49:58 2018 (r331962)
@@ -84,13 +84,6 @@ int intr_pic_ipi_setup(u_int, const char *, intr_ipi_h
#define NIRQ 288
#elif defined(CPU_ARM1176)
#define NIRQ 128
-#elif defined(SOC_MV_ARMADAXP)
-#define MAIN_IRQ_NUM 116
-#define ERR_IRQ_NUM 32
-#define ERR_IRQ (MAIN_IRQ_NUM)
-#define MSI_IRQ_NUM 32
-#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
-#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM)
#else
#define NIRQ 32
#endif
Modified: projects/krb5/sys/arm/mv/armada/wdt.c
==============================================================================
--- projects/krb5/sys/arm/mv/armada/wdt.c Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/mv/armada/wdt.c Tue Apr 3 22:49:58 2018 (r331962)
@@ -53,22 +53,54 @@ __FBSDID("$FreeBSD$");
#define INITIAL_TIMECOUNTER (0xffffffff)
#define MAX_WATCHDOG_TICKS (0xffffffff)
+#define WD_RST_OUT_EN 0x00000002
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
-#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
-#else
-#define MV_CLOCK_SRC get_tclk()
-#endif
+#define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
-#if defined(SOC_MV_ARMADA38X)
-#define WATCHDOG_TIMER 4
-#else
-#define WATCHDOG_TIMER 2
-#endif
+struct mv_wdt_config {
+ enum soc_family wdt_soc;
+ uint32_t wdt_timer;
+ void (*wdt_enable)(void);
+ void (*wdt_disable)(void);
+ unsigned int wdt_clock_src;
+};
+static void mv_wdt_enable_armv5(void);
+static void mv_wdt_enable_armada_38x(void);
+static void mv_wdt_enable_armada_xp(void);
+
+static void mv_wdt_disable_armv5(void);
+static void mv_wdt_disable_armada_38x(void);
+static void mv_wdt_disable_armada_xp(void);
+
+static struct mv_wdt_config mv_wdt_armada_38x_config = {
+ .wdt_soc = MV_SOC_ARMADA_38X,
+ .wdt_timer = 4,
+ .wdt_enable = &mv_wdt_enable_armada_38x,
+ .wdt_disable = &mv_wdt_disable_armada_38x,
+ .wdt_clock_src = MV_CLOCK_SRC_ARMV7,
+};
+
+static struct mv_wdt_config mv_wdt_armada_xp_config = {
+ .wdt_soc = MV_SOC_ARMADA_XP,
+ .wdt_timer = 2,
+ .wdt_enable = &mv_wdt_enable_armada_xp,
+ .wdt_disable = &mv_wdt_disable_armada_xp,
+ .wdt_clock_src = MV_CLOCK_SRC_ARMV7,
+};
+
+static struct mv_wdt_config mv_wdt_armv5_config = {
+ .wdt_soc = MV_SOC_ARMV5,
+ .wdt_timer = 2,
+ .wdt_enable = &mv_wdt_enable_armv5,
+ .wdt_disable = &mv_wdt_disable_armv5,
+ .wdt_clock_src = 0,
+};
+
struct mv_wdt_softc {
struct resource * wdt_res;
struct mtx wdt_mtx;
+ struct mv_wdt_config * wdt_config;
};
static struct resource_spec mv_wdt_spec[] = {
@@ -77,8 +109,10 @@ static struct resource_spec mv_wdt_spec[] = {
};
static struct ofw_compat_data mv_wdt_compat[] = {
- {"marvell,armada-380-wdt", true},
- {NULL, false}
+ {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config},
+ {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config},
+ {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config},
+ {NULL, (uintptr_t)NULL}
};
static struct mv_wdt_softc *wdt_softc = NULL;
@@ -91,8 +125,6 @@ static uint32_t mv_get_timer_control(void);
static void mv_set_timer_control(uint32_t);
static void mv_set_timer(uint32_t, uint32_t);
-static void mv_watchdog_enable(void);
-static void mv_watchdog_disable(void);
static void mv_watchdog_event(void *, unsigned int, int *);
static device_method_t mv_wdt_methods[] = {
@@ -145,7 +177,14 @@ mv_wdt_attach(device_t dev)
mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF);
- mv_watchdog_disable();
+ sc->wdt_config = (struct mv_wdt_config *)
+ ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data;
+
+ if (sc->wdt_config->wdt_clock_src == 0)
+ sc->wdt_config->wdt_clock_src = get_tclk();
+
+ if (wdt_softc->wdt_config->wdt_disable != NULL)
+ wdt_softc->wdt_config->wdt_disable();
EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
return (0);
@@ -171,20 +210,37 @@ mv_set_timer(uint32_t timer, uint32_t val)
bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val);
}
-
static void
-mv_watchdog_enable(void)
+mv_wdt_enable_armv5(void)
{
+ uint32_t val, irq_cause, irq_mask;
+
+ irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
+ irq_cause &= IRQ_TIMER_WD_CLR;
+ write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
+
+ irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
+ irq_mask |= IRQ_TIMER_WD_MASK;
+ write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
+
+ val = read_cpu_ctrl(RSTOUTn_MASK);
+ val |= WD_RST_OUT_EN;
+ write_cpu_ctrl(RSTOUTn_MASK, val);
+
+ val = mv_get_timer_control();
+ val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
+ mv_set_timer_control(val);
+}
+
+static inline void
+mv_wdt_enable_armada_38x_xp_helper()
+{
uint32_t val, irq_cause;
-#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
- uint32_t irq_mask;
-#endif
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER_WD_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
@@ -192,52 +248,41 @@ mv_watchdog_enable(void)
val = read_cpu_misc(RSTOUTn_MASK);
val &= ~RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, val);
-#else
- irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
- irq_mask |= IRQ_TIMER_WD_MASK;
- write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
+}
- val = read_cpu_ctrl(RSTOUTn_MASK);
- val |= WD_RST_OUT_EN;
- write_cpu_ctrl(RSTOUTn_MASK, val);
-#endif
+static void
+mv_wdt_enable_armada_38x(void)
+{
+ uint32_t val;
+ mv_wdt_enable_armada_38x_xp_helper();
+
val = mv_get_timer_control();
-#if defined(SOC_MV_ARMADA38X)
val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
-#elif defined(SOC_MV_ARMADAXP)
+ mv_set_timer_control(val);
+}
+
+static void
+mv_wdt_enable_armada_xp(void)
+{
+ uint32_t val;
+
+ mv_wdt_enable_armada_38x_xp_helper();
+
+ val = mv_get_timer_control();
val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
-#else
- val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
-#endif
mv_set_timer_control(val);
}
static void
-mv_watchdog_disable(void)
+mv_wdt_disable_armv5(void)
{
- uint32_t val, irq_cause;
-#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
- uint32_t irq_mask;
-#endif
+ uint32_t val, irq_cause, irq_mask;
val = mv_get_timer_control();
-#if defined(SOC_MV_ARMADA38X)
- val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
-#else
val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
-#endif
mv_set_timer_control(val);
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
- val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
- val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
- write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
-
- val = read_cpu_misc(RSTOUTn_MASK);
- val |= RSTOUTn_MASK_WD;
- write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
-#else
val = read_cpu_ctrl(RSTOUTn_MASK);
val &= ~WD_RST_OUT_EN;
write_cpu_ctrl(RSTOUTn_MASK, val);
@@ -245,13 +290,50 @@ mv_watchdog_disable(void)
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask &= ~(IRQ_TIMER_WD_MASK);
write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
-#endif
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER_WD_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
}
+static __inline void
+mv_wdt_disable_armada_38x_xp_helper(void)
+{
+ uint32_t val;
+
+ val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
+ val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
+ write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
+
+ val = read_cpu_misc(RSTOUTn_MASK);
+ val |= RSTOUTn_MASK_WD;
+ write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
+}
+
+static void
+mv_wdt_disable_armada_38x(void)
+{
+ uint32_t val;
+
+ val = mv_get_timer_control();
+ val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
+ mv_set_timer_control(val);
+
+ mv_wdt_disable_armada_38x_xp_helper();
+}
+
+static void
+mv_wdt_disable_armada_xp(void)
+{
+ uint32_t val;
+
+ val = mv_get_timer_control();
+ val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
+ mv_set_timer_control(val);
+
+ mv_wdt_disable_armada_38x_xp_helper();
+}
+
/*
* Watchdog event handler.
*/
@@ -264,20 +346,24 @@ mv_watchdog_event(void *arg, unsigned int cmd, int *er
sc = arg;
mtx_lock(&sc->wdt_mtx);
- if (cmd == 0)
- mv_watchdog_disable();
- else {
+ if (cmd == 0) {
+ if (wdt_softc->wdt_config->wdt_disable != NULL)
+ wdt_softc->wdt_config->wdt_disable();
+ } else {
/*
* Watchdog timeout is in nanosecs, calculation according to
* watchdog(9)
*/
ns = (uint64_t)1 << (cmd & WD_INTERVAL);
- ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
- if (ticks > MAX_WATCHDOG_TICKS)
- mv_watchdog_disable();
+ ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000;
+ if (ticks > MAX_WATCHDOG_TICKS) {
+ if (wdt_softc->wdt_config->wdt_disable != NULL)
+ wdt_softc->wdt_config->wdt_disable();
+ }
else {
- mv_set_timer(WATCHDOG_TIMER, ticks);
- mv_watchdog_enable();
+ mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks);
+ if (wdt_softc->wdt_config->wdt_enable != NULL)
+ wdt_softc->wdt_config->wdt_enable();
*error = 0;
}
}
Modified: projects/krb5/sys/arm/mv/armada38x/armada38x.c
==============================================================================
--- projects/krb5/sys/arm/mv/armada38x/armada38x.c Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/mv/armada38x/armada38x.c Tue Apr 3 22:49:58 2018 (r331962)
@@ -43,13 +43,25 @@ int armada38x_open_bootrom_win(void);
int armada38x_scu_enable(void);
int armada38x_win_set_iosync_barrier(void);
int armada38x_mbus_optimization(void);
+static uint64_t get_sar_value_armada38x(void);
static int hw_clockrate;
SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
&hw_clockrate, 0, "CPU instruction clock rate");
+static uint64_t
+get_sar_value_armada38x(void)
+{
+ uint32_t sar_low, sar_high;
+
+ sar_high = 0;
+ sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
+ SAMPLE_AT_RESET_ARMADA38X);
+ return (((uint64_t)sar_high << 32) | sar_low);
+}
+
uint32_t
-get_tclk(void)
+get_tclk_armada38x(void)
{
uint32_t sar;
@@ -57,8 +69,8 @@ get_tclk(void)
* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
* Current setting is read from Sample At Reset register.
*/
- sar = (uint32_t)get_sar_value();
- sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
+ sar = (uint32_t)get_sar_value_armada38x();
+ sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X;
if (sar == 0)
return (TCLK_250MHZ);
else
@@ -66,7 +78,7 @@ get_tclk(void)
}
uint32_t
-get_cpu_freq(void)
+get_cpu_freq_armada38x(void)
{
uint32_t sar;
@@ -78,7 +90,7 @@ get_cpu_freq(void)
1866, 0, 0, 2000
};
- sar = (uint32_t)get_sar_value();
+ sar = (uint32_t)get_sar_value_armada38x();
sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
if (sar >= nitems(cpu_frequencies))
return (0);
Modified: projects/krb5/sys/arm/mv/armada38x/std.armada38x
==============================================================================
--- projects/krb5/sys/arm/mv/armada38x/std.armada38x Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/mv/armada38x/std.armada38x Tue Apr 3 22:49:58 2018 (r331962)
@@ -1,6 +1,7 @@
# $FreeBSD$
files "../mv/armada38x/files.armada38x"
files "../mv/files.mv"
+files "../mv/files.arm7"
cpu CPU_CORTEXA
machine arm armv7
Modified: projects/krb5/sys/arm/mv/armadaxp/armadaxp.c
==============================================================================
--- projects/krb5/sys/arm/mv/armadaxp/armadaxp.c Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/mv/armadaxp/armadaxp.c Tue Apr 3 22:49:58 2018 (r331962)
@@ -55,6 +55,7 @@ static uint32_t count_l2clk(void);
void armadaxp_l2_init(void);
void armadaxp_init_coher_fabric(void);
int platform_get_ncpus(void);
+static uint64_t get_sar_value_armadaxp(void);
#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
#define ARMADAXP_L2_CTRL 0x100
@@ -124,8 +125,20 @@ static uint16_t cpu_clock_table[] = {
1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
2133, 2200, 2400 };
+static uint64_t
+get_sar_value_armadaxp(void)
+{
+ uint32_t sar_low, sar_high;
+
+ sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
+ SAMPLE_AT_RESET_HI);
+ sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
+ SAMPLE_AT_RESET_LO);
+ return (((uint64_t)sar_high << 32) | sar_low);
+}
+
uint32_t
-get_tclk(void)
+get_tclk_armadaxp(void)
{
uint32_t cputype;
@@ -139,7 +152,7 @@ get_tclk(void)
}
uint32_t
-get_cpu_freq(void)
+get_cpu_freq_armadaxp(void)
{
return (0);
@@ -153,7 +166,7 @@ count_l2clk(void)
uint8_t sar_cpu_freq, sar_fab_freq, array_size;
/* Get value of the SAR register and process it */
- sar_reg = get_sar_value();
+ sar_reg = get_sar_value_armadaxp();
sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
sar_fab_freq = FAB_FREQ_FIELD(sar_reg);
Copied: projects/krb5/sys/arm/mv/files.arm7 (from r331961, head/sys/arm/mv/files.arm7)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/krb5/sys/arm/mv/files.arm7 Tue Apr 3 22:49:58 2018 (r331962, copy of r331961, head/sys/arm/mv/files.arm7)
@@ -0,0 +1,3 @@
+# $FreeBSD$
+arm/mv/armada38x/armada38x.c standard
+arm/mv/armadaxp/armadaxp.c standard
Modified: projects/krb5/sys/arm/mv/mpic.c
==============================================================================
--- projects/krb5/sys/arm/mv/mpic.c Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/mv/mpic.c Tue Apr 3 22:49:58 2018 (r331962)
@@ -103,12 +103,10 @@ __FBSDID("$FreeBSD$");
#define MPIC_PPI 32
-#ifdef INTRNG
struct mv_mpic_irqsrc {
struct intr_irqsrc mmi_isrc;
u_int mmi_irq;
};
-#endif
struct mv_mpic_softc {
device_t sc_dev;
@@ -120,9 +118,7 @@ struct mv_mpic_softc {
bus_space_tag_t drbl_bst;
bus_space_handle_t drbl_bsh;
struct mtx mtx;
-#ifdef INTRNG
struct mv_mpic_irqsrc * mpic_isrcs;
-#endif
int nirqs;
void * intr_hand;
};
@@ -155,10 +151,12 @@ static void mpic_mask_irq(uintptr_t nb);
static void mpic_mask_irq_err(uintptr_t nb);
static void mpic_unmask_irq_err(uintptr_t nb);
static boolean_t mpic_irq_is_percpu(uintptr_t);
-#ifdef INTRNG
static int mpic_intr(void *arg);
-#endif
static void mpic_unmask_msi(void);
+void mpic_init_secondary(device_t);
+void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
+int mpic_ipi_read(int);
+void mpic_ipi_clear(int);
#define MPIC_WRITE(softc, reg, val) \
bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
@@ -189,7 +187,6 @@ mv_mpic_probe(device_t dev)
return (0);
}
-#ifdef INTRNG
static int
mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
{
@@ -221,7 +218,6 @@ mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
}
return (0);
}
-#endif
static int
mv_mpic_attach(device_t dev)
@@ -246,13 +242,11 @@ mv_mpic_attach(device_t dev)
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
-#ifdef INTRNG
if (sc->mpic_res[3] == NULL)
device_printf(dev, "No interrupt to use.\n");
else
bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
mpic_intr, NULL, sc, &sc->intr_hand);
-#endif
sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
@@ -272,7 +266,6 @@ mv_mpic_attach(device_t dev)
val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
sc->nirqs = MPIC_CTRL_NIRQS(val);
-#ifdef INTRNG
if (mv_mpic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
@@ -286,7 +279,6 @@ mv_mpic_attach(device_t dev)
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);
}
-#endif
mpic_unmask_msi();
@@ -299,7 +291,6 @@ mv_mpic_attach(device_t dev)
return (0);
}
-#ifdef INTRNG
static int
mpic_intr(void *arg)
{
@@ -386,20 +377,19 @@ static void
mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
{
}
-#endif
static device_method_t mv_mpic_methods[] = {
DEVMETHOD(device_probe, mv_mpic_probe),
DEVMETHOD(device_attach, mv_mpic_attach),
-#ifdef INTRNG
DEVMETHOD(pic_disable_intr, mpic_disable_intr),
DEVMETHOD(pic_enable_intr, mpic_enable_intr),
DEVMETHOD(pic_map_intr, mpic_map_intr),
DEVMETHOD(pic_post_filter, mpic_post_filter),
DEVMETHOD(pic_post_ithread, mpic_post_ithread),
DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),
-#endif
+ DEVMETHOD(pic_init_secondary, mpic_init_secondary),
+ DEVMETHOD(pic_ipi_send, mpic_ipi_send),
{ 0, 0 }
};
@@ -414,46 +404,6 @@ static devclass_t mv_mpic_devclass;
EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
-#ifndef INTRNG
-int
-arm_get_next_irq(int last)
-{
- u_int irq, next = -1;
-
- irq = mv_mpic_get_cause() & MPIC_IRQ_MASK;
- CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq);
-
- if (irq != MPIC_IRQ_MASK) {
- if (irq == MPIC_INT_ERR)
- irq = mv_mpic_get_cause_err();
- if (irq == MPIC_INT_MSI)
- irq = mv_mpic_get_msi();
- next = irq;
- }
-
- CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
- return (next);
-}
-
-/*
- * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only
- * by ISM/ICM and remove access to ICE in masking operation
- */
-void
-arm_mask_irq(uintptr_t nb)
-{
-
- mpic_mask_irq(nb);
-}
-
-void
-arm_unmask_irq(uintptr_t nb)
-{
-
- mpic_unmask_irq(nb);
-}
-#endif
-
static void
mpic_unmask_msi(void)
{
@@ -621,15 +571,13 @@ mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
return (0);
}
-
-#if defined(SMP) && defined(SOC_MV_ARMADAXP)
void
-intr_pic_init_secondary(void)
+mpic_init_secondary(device_t dev)
{
}
void
-pic_ipi_send(cpuset_t cpus, u_int ipi)
+mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
{
uint32_t val, i;
@@ -642,7 +590,7 @@ pic_ipi_send(cpuset_t cpus, u_int ipi)
}
int
-pic_ipi_read(int i __unused)
+mpic_ipi_read(int i __unused)
{
uint32_t val;
int ipi;
@@ -658,8 +606,6 @@ pic_ipi_read(int i __unused)
}
void
-pic_ipi_clear(int ipi)
+mpic_ipi_clear(int ipi)
{
}
-
-#endif
Modified: projects/krb5/sys/arm/mv/mv_common.c
==============================================================================
--- projects/krb5/sys/arm/mv/mv_common.c Tue Apr 3 22:21:12 2018 (r331961)
+++ projects/krb5/sys/arm/mv/mv_common.c Tue Apr 3 22:49:58 2018 (r331962)
@@ -76,6 +76,19 @@ MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
#define MV_DUMP_WIN 0
#endif
+static enum soc_family soc_family;
+
+static int mv_win_cesa_attr(int wng_sel);
+static int mv_win_cesa_attr_armv5(int eng_sel);
+static int mv_win_cesa_attr_armada38x(int eng_sel);
+static int mv_win_cesa_attr_armadaxp(int eng_sel);
+
+uint32_t read_cpu_ctrl_armv5(uint32_t reg);
+uint32_t read_cpu_ctrl_armv7(uint32_t reg);
+
+void write_cpu_ctrl_armv5(uint32_t reg, uint32_t val);
+void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val);
+
static int win_eth_can_remap(int i);
static int decode_win_cesa_valid(void);
@@ -91,9 +104,7 @@ static int decode_win_idma_valid(void);
static int decode_win_xor_valid(void);
static void decode_win_cpu_setup(void);
-#ifdef SOC_MV_ARMADAXP
static int decode_win_sdram_fixup(void);
-#endif
static void decode_win_cesa_setup(u_long);
static void decode_win_usb_setup(u_long);
static void decode_win_usb3_setup(u_long);
@@ -117,11 +128,48 @@ static void decode_win_ahci_dump(u_long base);
static void decode_win_sdhci_dump(u_long);
static void decode_win_pcie_dump(u_long);
+static uint32_t win_cpu_cr_read(int);
+static uint32_t win_cpu_armv5_cr_read(int);
+static uint32_t win_cpu_armv7_cr_read(int);
+static uint32_t win_cpu_br_read(int);
+static uint32_t win_cpu_armv5_br_read(int);
+static uint32_t win_cpu_armv7_br_read(int);
+static uint32_t win_cpu_remap_l_read(int);
+static uint32_t win_cpu_armv5_remap_l_read(int);
+static uint32_t win_cpu_armv7_remap_l_read(int);
+static uint32_t win_cpu_remap_h_read(int);
+static uint32_t win_cpu_armv5_remap_h_read(int);
+static uint32_t win_cpu_armv7_remap_h_read(int);
+
+static void win_cpu_cr_write(int, uint32_t);
+static void win_cpu_armv5_cr_write(int, uint32_t);
+static void win_cpu_armv7_cr_write(int, uint32_t);
+static void win_cpu_br_write(int, uint32_t);
+static void win_cpu_armv5_br_write(int, uint32_t);
+static void win_cpu_armv7_br_write(int, uint32_t);
+static void win_cpu_remap_l_write(int, uint32_t);
+static void win_cpu_armv5_remap_l_write(int, uint32_t);
+static void win_cpu_armv7_remap_l_write(int, uint32_t);
+static void win_cpu_remap_h_write(int, uint32_t);
+static void win_cpu_armv5_remap_h_write(int, uint32_t);
+static void win_cpu_armv7_remap_h_write(int, uint32_t);
+
+static uint32_t ddr_br_read(int);
+static uint32_t ddr_sz_read(int);
+static uint32_t ddr_armv5_br_read(int);
+static uint32_t ddr_armv5_sz_read(int);
+static uint32_t ddr_armv7_br_read(int);
+static uint32_t ddr_armv7_sz_read(int);
+static void ddr_br_write(int, uint32_t);
+static void ddr_sz_write(int, uint32_t);
+static void ddr_armv5_br_write(int, uint32_t);
+static void ddr_armv5_sz_write(int, uint32_t);
+static void ddr_armv7_br_write(int, uint32_t);
+static void ddr_armv7_sz_write(int, uint32_t);
+
static int fdt_get_ranges(const char *, void *, int, int *, int *);
-#ifdef SOC_MV_ARMADA38X
int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
int *trig, int *pol);
-#endif
static int win_cpu_from_dt(void);
static int fdt_win_setup(void);
@@ -138,6 +186,7 @@ const struct decode_win *cpu_wins = cpu_win_tbl;
typedef void (*decode_win_setup_t)(u_long);
typedef void (*dump_win_t)(u_long);
+typedef int (*valid_t)(void);
/*
* The power status of device feature is only supported on
@@ -153,24 +202,135 @@ struct soc_node_spec {
const char *compat;
decode_win_setup_t decode_handler;
dump_win_t dump_handler;
+ valid_t valid_handler;
};
static struct soc_node_spec soc_nodes[] = {
- { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
- { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump },
- { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
- { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
- { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
- { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump },
- { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump },
- { "mrvl,sata", &decode_win_sata_setup, NULL },
- { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
- { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
- { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump },
- { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump },
- { NULL, NULL, NULL },
+ { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump, &decode_win_eth_valid},
+ { "marvell,armada-370-neta", &decode_win_neta_setup,
+ &decode_win_neta_dump, NULL },
+ { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid},
+ { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid },
+ { "marvell,armada-380-xhci", &decode_win_usb3_setup,
+ &decode_win_usb3_dump, &decode_win_usb3_valid },
+ { "marvell,armada-380-ahci", &decode_win_ahci_setup,
+ &decode_win_ahci_dump, NULL },
+ { "marvell,armada-380-sdhci", &decode_win_sdhci_setup,
+ &decode_win_sdhci_dump, &decode_win_sdhci_valid},
+ { "mrvl,sata", &decode_win_sata_setup, NULL, &decode_win_sata_valid},
+ { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump, &decode_win_xor_valid},
+ { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump, &decode_win_idma_valid},
+ { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump, &decode_win_cesa_valid},
+ { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump, &decode_win_pcie_valid},
+ { NULL, NULL, NULL, NULL },
};
+typedef uint32_t(*read_cpu_ctrl_t)(uint32_t);
+typedef void(*write_cpu_ctrl_t)(uint32_t, uint32_t);
+typedef uint32_t (*win_read_t)(int);
+typedef void (*win_write_t)(int, uint32_t);
+typedef int (*win_cesa_attr_t)(int);
+typedef uint32_t (*get_t)(void);
+
+struct decode_win_spec {
+ read_cpu_ctrl_t read_cpu_ctrl;
+ write_cpu_ctrl_t write_cpu_ctrl;
+ win_read_t cr_read;
+ win_read_t br_read;
+ win_read_t remap_l_read;
+ win_read_t remap_h_read;
+ win_write_t cr_write;
+ win_write_t br_write;
+ win_write_t remap_l_write;
+ win_write_t remap_h_write;
+ uint32_t mv_win_cpu_max;
+ win_cesa_attr_t win_cesa_attr;
+ int win_cesa_target;
+ win_read_t ddr_br_read;
+ win_read_t ddr_sz_read;
+ win_write_t ddr_br_write;
+ win_write_t ddr_sz_write;
+#if __ARM_ARCH >= 6
+ get_t get_tclk;
+ get_t get_cpu_freq;
+#endif
+};
+
+struct decode_win_spec *soc_decode_win_spec;
+
+static struct decode_win_spec decode_win_specs[] =
+{
+ {
+ &read_cpu_ctrl_armv7,
+ &write_cpu_ctrl_armv7,
+ &win_cpu_armv7_cr_read,
+ &win_cpu_armv7_br_read,
+ &win_cpu_armv7_remap_l_read,
+ &win_cpu_armv7_remap_h_read,
+ &win_cpu_armv7_cr_write,
+ &win_cpu_armv7_br_write,
+ &win_cpu_armv7_remap_l_write,
+ &win_cpu_armv7_remap_h_write,
+ MV_WIN_CPU_MAX_ARMV7,
+ &mv_win_cesa_attr_armada38x,
+ MV_WIN_CESA_TARGET_ARMADA38X,
+ &ddr_armv7_br_read,
+ &ddr_armv7_sz_read,
+ &ddr_armv7_br_write,
+ &ddr_armv7_sz_write,
+#if __ARM_ARCH >= 6
+ &get_tclk_armada38x,
+ &get_cpu_freq_armada38x,
+#endif
+ },
+ {
+ &read_cpu_ctrl_armv7,
+ &write_cpu_ctrl_armv7,
+ &win_cpu_armv7_cr_read,
+ &win_cpu_armv7_br_read,
+ &win_cpu_armv7_remap_l_read,
+ &win_cpu_armv7_remap_h_read,
+ &win_cpu_armv7_cr_write,
+ &win_cpu_armv7_br_write,
+ &win_cpu_armv7_remap_l_write,
+ &win_cpu_armv7_remap_h_write,
+ MV_WIN_CPU_MAX_ARMV7,
+ &mv_win_cesa_attr_armadaxp,
+ MV_WIN_CESA_TARGET_ARMADAXP,
+ &ddr_armv7_br_read,
+ &ddr_armv7_sz_read,
+ &ddr_armv7_br_write,
+ &ddr_armv7_sz_write,
+#if __ARM_ARCH >= 6
+ &get_tclk_armadaxp,
+ &get_cpu_freq_armadaxp,
+#endif
+ },
+ {
+ &read_cpu_ctrl_armv5,
+ &write_cpu_ctrl_armv5,
+ &win_cpu_armv5_cr_read,
+ &win_cpu_armv5_br_read,
+ &win_cpu_armv5_remap_l_read,
+ &win_cpu_armv5_remap_h_read,
+ &win_cpu_armv5_cr_write,
+ &win_cpu_armv5_br_write,
+ &win_cpu_armv5_remap_l_write,
+ &win_cpu_armv5_remap_h_write,
+ MV_WIN_CPU_MAX,
+ &mv_win_cesa_attr_armv5,
+ MV_WIN_CESA_TARGET,
+ &ddr_armv5_br_read,
+ &ddr_armv5_sz_read,
+ &ddr_armv5_br_write,
+ &ddr_armv5_sz_write,
+#if __ARM_ARCH >= 6
+ NULL,
+ NULL,
+#endif
+ },
+};
+
struct fdt_pm_mask_entry {
char *compat;
uint32_t mask;
@@ -231,6 +391,74 @@ pm_is_disabled(uint32_t mask)
* This feature can be used only on Kirkwood and Discovery
* machines.
*/
+
+static int mv_win_cesa_attr(int eng_sel)
+{
+
+ if (soc_decode_win_spec->win_cesa_attr != NULL)
+ return (soc_decode_win_spec->win_cesa_attr(eng_sel));
+
+ return (-1);
+}
+
+static int mv_win_cesa_attr_armv5(int eng_sel)
+{
+
+ return MV_WIN_CESA_ATTR(eng_sel);
+}
+
+static int mv_win_cesa_attr_armada38x(int eng_sel)
+{
+
+ return MV_WIN_CESA_ATTR_ARMADA38X(eng_sel);
+}
+
+static int mv_win_cesa_attr_armadaxp(int eng_sel)
+{
+
+ return MV_WIN_CESA_ATTR_ARMADAXP(eng_sel);
+}
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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