svn commit: r283030 - in projects/ci20_mips/sys/mips: conf ingenic
Sean Bruno
sbruno at FreeBSD.org
Sun May 17 16:14:51 UTC 2015
Author: sbruno
Date: Sun May 17 16:14:48 2015
New Revision: 283030
URL: https://svnweb.freebsd.org/changeset/base/283030
Log:
Begin support for Imagination Tech CI20 Creator Board.
Add netbsd files to support devices (untested, does not compile).
Add basic kernconf, more or less a copy of MALTA.
Sponsored by: Imagination Tech
Added:
projects/ci20_mips/sys/mips/conf/CI20
projects/ci20_mips/sys/mips/ingenic/
projects/ci20_mips/sys/mips/ingenic/apbus.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/files.ingenic
projects/ci20_mips/sys/mips/ingenic/ingenic_com.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_dme.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_dwctwo.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_ehci.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_machdep.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_ohci.c (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_regs.h (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/ingenic_var.h (contents, props changed)
projects/ci20_mips/sys/mips/ingenic/jziic.c (contents, props changed)
Added: projects/ci20_mips/sys/mips/conf/CI20
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/conf/CI20 Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,37 @@
+# $FreeBSD: $
+
+machine mips mips
+cpu CPU_MIPS74KC
+ident CI20
+machine mips mips
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+
+
+files "../ingenic/files.ingenic"
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Debugging for use in -current
+options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+options WITNESS #Enable checks to detect deadlocks and cycles
+options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device loop
+device ether
+device md
Added: projects/ci20_mips/sys/mips/ingenic/apbus.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/ingenic/apbus.c Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,275 @@
+/* $NetBSD: apbus.c,v 1.14 2015/05/04 12:23:15 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* catch-all for on-chip peripherals */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.14 2015/05/04 12:23:15 macallan Exp $");
+
+#include "locators.h"
+#define _MIPS_BUS_DMA_PRIVATE
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/extent.h>
+#include <sys/systm.h>
+
+#include <mips/ingenic/ingenic_var.h>
+#include <mips/ingenic/ingenic_regs.h>
+
+#include "opt_ingenic.h"
+
+static int apbus_match(device_t, cfdata_t, void *);
+static void apbus_attach(device_t, device_t, void *);
+static int apbus_print(void *, const char *);
+static void apbus_bus_mem_init(bus_space_tag_t, void *);
+
+CFATTACH_DECL_NEW(apbus, 0, apbus_match, apbus_attach, NULL, NULL);
+
+static struct mips_bus_space apbus_mbst;
+bus_space_tag_t apbus_memt = NULL;
+
+struct mips_bus_dma_tag apbus_dmat = {
+ ._bounce_alloc_hi = 0x10000000,
+ ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
+ ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
+ ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
+};
+
+typedef struct apbus_dev {
+ const char *name; /* driver name */
+ bus_addr_t addr; /* base address */
+ uint32_t irq; /* interrupt */
+ uint32_t clk0; /* bit(s) in CLKGR0 */
+ uint32_t clk1; /* bit(s) in CLKGR1 */
+} apbus_dev_t;
+
+static const apbus_dev_t apbus_devs[] = {
+ { "dwctwo", JZ_DWC2_BASE, 21, CLK_OTG0 | CLK_UHC, CLK_OTG1},
+ { "ohci", JZ_OHCI_BASE, 5, CLK_UHC, 0},
+ { "ehci", JZ_EHCI_BASE, 20, CLK_UHC, 0},
+ { "dme", JZ_DME_BASE, -1, 0, 0},
+ { "jzgpio", JZ_GPIO_A_BASE, 17, 0, 0},
+ { "jzgpio", JZ_GPIO_B_BASE, 16, 0, 0},
+ { "jzgpio", JZ_GPIO_C_BASE, 15, 0, 0},
+ { "jzgpio", JZ_GPIO_D_BASE, 14, 0, 0},
+ { "jzgpio", JZ_GPIO_E_BASE, 13, 0, 0},
+ { "jzgpio", JZ_GPIO_F_BASE, 12, 0, 0},
+ { "jziic", JZ_SMB0_BASE, 60, CLK_SMB0, 0},
+ { "jziic", JZ_SMB1_BASE, 59, CLK_SMB1, 0},
+ { "jziic", JZ_SMB2_BASE, 58, CLK_SMB2, 0},
+ { "jziic", JZ_SMB3_BASE, 57, 0, CLK_SMB3},
+ { "jziic", JZ_SMB4_BASE, 56, 0, CLK_SMB4},
+ { "jzmmc", JZ_MSC0_BASE, 37, CLK_MSC0, 0},
+ { "jzmmc", JZ_MSC1_BASE, 36, CLK_MSC1, 0},
+ { "jzmmc", JZ_MSC2_BASE, 35, CLK_MSC2, 0},
+ { "jzfb", JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI},
+ { NULL, -1, -1, 0, 0}
+};
+
+void
+apbus_init(void)
+{
+ static bool done = false;
+ if (done)
+ return;
+ done = true;
+
+ apbus_bus_mem_init(&apbus_mbst, NULL);
+ apbus_memt = &apbus_mbst;
+}
+
+int
+apbus_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct mainbusdev {
+ const char *md_name;
+ } *aa = aux;
+ if (strcmp(aa->md_name, "apbus") == 0) return 1;
+ return 0;
+}
+
+void
+apbus_attach(device_t parent, device_t self, void *aux)
+{
+ uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv;
+ aprint_normal("\n");
+
+ /* should have been called early on */
+ apbus_init();
+
+#ifdef INGENIC_DEBUG
+ printf("core ctrl: %08x\n", MFC0(12, 2));
+ printf("core status: %08x\n", MFC0(12, 3));
+ printf("REIM: %08x\n", MFC0(12, 4));
+ printf("ID: %08x\n", MFC0(15, 1));
+#endif
+ /* assuming we're using MPLL */
+ mpll = readreg(JZ_CPMPCR);
+ m = (mpll & JZ_PLLM_M) >> JZ_PLLM_S;
+ n = (mpll & JZ_PLLN_M) >> JZ_PLLN_S;
+ p = (mpll & JZ_PLLP_M) >> JZ_PLLP_S;
+
+ /* assuming 48MHz EXTCLK */
+ mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
+
+ reg = readreg(JZ_CPCCR);
+ pdiv = ((reg & JZ_PDIV_M) >> JZ_PDIV_S) + 1;
+ pclk = mclk / pdiv;
+ cdiv = (reg & JZ_CDIV_M) + 1;
+ cclk = mclk / cdiv;
+
+ aprint_debug_dev(self, "mclk %d kHz\n", mclk);
+ aprint_debug_dev(self, "pclk %d kHz\n", pclk);
+ aprint_debug_dev(self, "CPU clock %d kHz\n", cclk);
+
+ /* enable clocks */
+ reg = readreg(JZ_CLKGR1);
+ reg &= ~CLK_AHB_MON; /* AHB_MON clock */
+ writereg(JZ_CLKGR1, reg);
+
+ /* wake up the USB part */
+ reg = readreg(JZ_OPCR);
+ reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
+ writereg(JZ_OPCR, reg);
+
+ /* wire up GPIOs */
+ /* iic0 */
+ gpio_as_dev0(3, 30);
+ gpio_as_dev0(3, 31);
+ /* iic1 */
+ gpio_as_dev0(4, 30);
+ gpio_as_dev0(4, 31);
+ /* iic2 */
+ gpio_as_dev2(5, 16);
+ gpio_as_dev2(5, 17);
+ /* iic3 */
+ gpio_as_dev1(3, 10);
+ gpio_as_dev1(3, 11);
+ /* iic4 */
+ /* make sure these aren't SMB4 */
+ gpio_as_dev3(4, 3);
+ gpio_as_dev3(4, 4);
+ /* these are supposed to be connected to the RTC */
+ gpio_as_dev1(4, 12);
+ gpio_as_dev1(4, 13);
+ /* these can be DDC2 or SMB4, set them to DDC2 */
+ gpio_as_dev0(5, 24);
+ gpio_as_dev0(5, 25);
+
+ /* MSC0 */
+ gpio_as_dev1(0, 4);
+ gpio_as_dev1(0, 5);
+ gpio_as_dev1(0, 6);
+ gpio_as_dev1(0, 7);
+ gpio_as_dev1(0, 18);
+ gpio_as_dev1(0, 19);
+ gpio_as_dev1(0, 20);
+ gpio_as_dev1(0, 21);
+ gpio_as_dev1(0, 22);
+ gpio_as_dev1(0, 23);
+ gpio_as_dev1(0, 24);
+ gpio_as_intr_level_low(5, 20); /* card detect */
+
+ /* MSC1, for wifi/bt */
+ gpio_as_dev0(3, 20);
+ gpio_as_dev0(3, 21);
+ gpio_as_dev0(3, 22);
+ gpio_as_dev0(3, 23);
+ gpio_as_dev0(3, 24);
+ gpio_as_dev0(3, 25);
+
+ /* MSC2, on expansion header */
+ gpio_as_dev0(1, 20);
+ gpio_as_dev0(1, 21);
+ gpio_as_dev0(1, 28);
+ gpio_as_dev0(1, 29);
+ gpio_as_dev0(1, 30);
+ gpio_as_dev0(1, 31);
+
+#ifdef INGENIC_DEBUG
+ printf("JZ_CLKGR0 %08x\n", readreg(JZ_CLKGR0));
+ printf("JZ_CLKGR1 %08x\n", readreg(JZ_CLKGR1));
+ printf("JZ_SPCR0 %08x\n", readreg(JZ_SPCR0));
+ printf("JZ_SPCR1 %08x\n", readreg(JZ_SPCR1));
+ printf("JZ_SRBC %08x\n", readreg(JZ_SRBC));
+ printf("JZ_OPCR %08x\n", readreg(JZ_OPCR));
+ printf("JZ_UHCCDR %08x\n", readreg(JZ_UHCCDR));
+#endif
+
+ for (const apbus_dev_t *adv = apbus_devs; adv->name != NULL; adv++) {
+ struct apbus_attach_args aa;
+ aa.aa_name = adv->name;
+ aa.aa_addr = adv->addr;
+ aa.aa_irq = adv->irq;
+ aa.aa_dmat = &apbus_dmat;
+ aa.aa_bst = apbus_memt;
+ aa.aa_pclk = pclk;
+ aa.aa_mclk = mclk;
+
+ /* enable clocks as needed */
+ if (adv->clk0 != 0) {
+ reg = readreg(JZ_CLKGR0);
+ reg &= ~adv->clk0;
+ writereg(JZ_CLKGR0, reg);
+ }
+
+ if (adv->clk1 != 0) {
+ reg = readreg(JZ_CLKGR1);
+ reg &= ~adv->clk1;
+ writereg(JZ_CLKGR1, reg);
+ }
+
+ (void) config_found_ia(self, "apbus", &aa, apbus_print);
+ }
+}
+
+int
+apbus_print(void *aux, const char *pnp)
+{
+ struct apbus_attach_args *aa = aux;
+
+ if (pnp) {
+ aprint_normal("%s at %s", aa->aa_name, pnp);
+ }
+ if (aa->aa_addr != -1)
+ aprint_normal(" addr 0x%" PRIxBUSADDR, aa->aa_addr);
+ if ((pnp == NULL) && (aa->aa_irq != -1))
+ aprint_normal(" irq %d", aa->aa_irq);
+ return (UNCONF);
+}
+
+#define CHIP apbus
+#define CHIP_MEM /* defined */
+#define CHIP_W1_BUS_START(v) 0x10000000UL
+#define CHIP_W1_BUS_END(v) 0x20000000UL
+#define CHIP_W1_SYS_START(v) 0x10000000UL
+#define CHIP_W1_SYS_END(v) 0x20000000UL
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Added: projects/ci20_mips/sys/mips/ingenic/files.ingenic
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/ingenic/files.ingenic Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,15 @@
+# $FreeBSD: $
+
+mips/ingenic/apbus.c optional ingenic_abp
+mips/ingenic/ingenic_com.c optional uart_ignenic
+mips/ingenic/ingenic_dwctwo.c optional test
+mips/ingenic/ingenic_ohci.c optional test
+mips/ingenic/ingenic_ehci.c optional test
+mips/ingenic/ingenic_dme.c optional test
+mips/ingenic/jziic.c optional test
+
+mips/ingenic/ingenic_machdep.c standard
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
+
+dev/hwpmc/hwpmc_mips24k.c optional hwpmc_mips24k
Added: projects/ci20_mips/sys/mips/ingenic/ingenic_com.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/ingenic/ingenic_com.c Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,205 @@
+/* $NetBSD: ingenic_com.c,v 1.4 2015/03/07 15:35:33 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ingenic_com.c,v 1.4 2015/03/07 15:35:33 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/termios.h>
+#include <sys/ttydefaults.h>
+#include <sys/types.h>
+
+#include <sys/bus.h>
+
+#include <dev/cons.h>
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <mips/cpuregs.h>
+
+#include <mips/ingenic/ingenic_regs.h>
+
+#include "opt_com.h"
+
+volatile int32_t *com0addr = (int32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
+
+void ingenic_putchar_init(void);
+void ingenic_puts(const char *);
+void ingenic_putchar(char);
+
+#ifndef CONMODE
+# define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8)
+#endif
+
+
+static struct mips_bus_space ingenic_com_mbst;
+static int mbst_valid = 0;
+static void ingenic_com_bus_mem_init(bus_space_tag_t, void *);
+void ingenic_com_cnattach(void);
+
+static int ingenic_com_match(device_t, cfdata_t , void *);
+static void ingenic_com_attach(device_t, device_t, void *);
+
+struct ingenic_com_softc {
+ struct com_softc sc_com;
+};
+
+CFATTACH_DECL_NEW(com_mainbus, sizeof(struct ingenic_com_softc),
+ ingenic_com_match, ingenic_com_attach, NULL, NULL);
+
+bus_space_handle_t regh = 0;
+
+void
+ingenic_putchar_init(void)
+{
+ /*
+ * XXX don't screw with the UART's speed until we know what clock
+ * we're on
+ */
+#if 0
+ int rate;
+#endif
+ extern int comspeed(long, long, int);
+
+ com0addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
+#if 0
+ if (comcnfreq != -1) {
+ rate = comspeed(comcnspeed, comcnfreq, COM_TYPE_INGENIC);
+ if (rate < 0)
+ return; /* XXX */
+#endif
+ com0addr[com_ier] = 0;
+ com0addr[com_lctl] = htole32(LCR_DLAB);
+#if 0
+ com0addr[com_dlbl] = htole32(rate & 0xff);
+ com0addr[com_dlbh] = htole32(rate >> 8);
+#endif
+ com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */
+ com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS);
+ com0addr[com_fifo] = htole32(
+ FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
+ FIFO_TRIGGER_1 | FIFO_UART_ON);
+#if 0
+ }
+#endif
+}
+
+
+void
+ingenic_putchar(char c)
+{
+ int timo = 150000;
+
+ while ((le32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0)
+ if (--timo == 0)
+ break;
+
+ com0addr[com_data] = htole32((uint32_t)c);
+
+ while ((le32toh(com0addr[com_lsr]) & LSR_TSRE) == 0)
+ if (--timo == 0)
+ break;
+}
+
+void
+ingenic_puts(const char *restrict s)
+{
+ char c;
+
+ while ((c = *s++) != 0)
+ ingenic_putchar(c);
+}
+
+static void
+ingenic_com_bus_init(void)
+{
+ if (mbst_valid) return;
+ ingenic_com_bus_mem_init(&ingenic_com_mbst, NULL);
+ mbst_valid = 1;
+}
+
+void
+ingenic_com_cnattach(void)
+{
+ struct com_regs regs;
+
+ ingenic_com_bus_init();
+ bus_space_map(&ingenic_com_mbst, 0, 0x1000, 0, ®h);
+
+ memset(®s, 0, sizeof(regs));
+ COM_INIT_REGS(regs, &ingenic_com_mbst, regh, 0);
+
+ /*
+ * XXX
+ * UART clock is either 6MHz or 12MHz, the manual is rather unclear
+ * so we just leave alone whatever u-boot set up
+ * my uplcom is too tolerant to show any difference
+ */
+ comcnattach1(®s, 115200, 48000000, COM_TYPE_INGENIC, CONMODE);
+}
+
+static int
+ingenic_com_match(device_t parent, cfdata_t cfdata, void *args)
+{
+ struct mainbusdev {
+ const char *md_name;
+ } *aa = args;
+ if (strcmp(aa->md_name, "com") == 0) return 1;
+ return 0;
+}
+
+
+static void
+ingenic_com_attach(device_t parent, device_t self, void *args)
+{
+ struct ingenic_com_softc *isc = device_private(self);
+ struct com_softc *sc = &isc->sc_com;
+
+ sc->sc_dev = self;
+ sc->sc_frequency = 48000000;
+ sc->sc_type = COM_TYPE_INGENIC;
+ memset(&sc->sc_regs, 0, sizeof(sc->sc_regs));
+ COM_INIT_REGS(sc->sc_regs, &ingenic_com_mbst, regh, 0);
+ com_attach_subr(sc);
+ printf("\n");
+ evbmips_intr_establish(51, comintr, sc);
+}
+
+#define CHIP ingenic_com
+#define CHIP_MEM /* defined */
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0x00010000UL
+#define CHIP_W1_SYS_START(v) 0x10030000UL
+#define CHIP_W1_SYS_END(v) 0x10035000UL
+#define CHIP_ACCESS_SIZE 1
+#define CHIP_ALIGN_STRIDE 2
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Added: projects/ci20_mips/sys/mips/ingenic/ingenic_dme.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/ingenic/ingenic_dme.c Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,165 @@
+/* $NetBSD: ingenic_dme.c,v 1.1 2015/03/10 18:15:47 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2015 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.1 2015/03/10 18:15:47 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/workqueue.h>
+
+#include <mips/ingenic/ingenic_var.h>
+#include <mips/ingenic/ingenic_regs.h>
+
+#include <net/if.h>
+#include <net/if_ether.h>
+#include <net/if_media.h>
+
+#include <dev/ic/dm9000var.h>
+#include <dev/ic/dm9000reg.h>
+
+#include "opt_ingenic.h"
+
+static int ingenic_dme_match(device_t, struct cfdata *, void *);
+static void ingenic_dme_attach(device_t, device_t, void *);
+static int ingenic_dme_intr(void *);
+
+CFATTACH_DECL_NEW(ingenic_dme, sizeof(struct dme_softc),
+ ingenic_dme_match, ingenic_dme_attach, NULL, NULL);
+
+#define GPIO_DME_INT 19
+#define GPIO_DME_INT_MASK (1 << GPIO_DME_INT)
+
+/* ARGSUSED */
+static int
+ingenic_dme_match(device_t parent, struct cfdata *match, void *aux)
+{
+ struct apbus_attach_args *aa = aux;
+
+ if (strcmp(aa->aa_name, "dme") != 0)
+ return 0;
+
+ return 1;
+}
+
+/* ARGSUSED */
+static void
+ingenic_dme_attach(device_t parent, device_t self, void *aux)
+{
+ struct dme_softc *sc = device_private(self);
+ struct apbus_attach_args *aa = aux;
+ void *ih;
+ static uint8_t enaddr[ETHER_ADDR_LEN];
+ int error;
+
+ sc->sc_dev = self;
+
+ sc->sc_iot = aa->aa_bst;
+ sc->dme_io = JZ_DME_IO;
+ sc->dme_data = JZ_DME_DATA;
+ sc->sc_phy_initialized = 0;
+
+ if (aa->aa_addr == 0)
+ aa->aa_addr = JZ_DME_BASE;
+
+ error = bus_space_map(aa->aa_bst, aa->aa_addr, 4, 0, &sc->sc_ioh);
+ if (error) {
+ aprint_error_dev(self,
+ "can't map registers for %s: %d\n", aa->aa_name, error);
+ return;
+ }
+
+ aprint_naive(": DM9000 Ethernet controller\n");
+ aprint_normal(": DM9000 Ethernet controller\n");
+
+
+ /* make sure the chip is powered up and not in reset */
+ gpio_as_output(1, 25);
+ gpio_set(1, 25, 1);
+ gpio_as_output(5, 12);
+ gpio_set(5, 12, 1);
+
+ /* setup pins to talk to the chip */
+ gpio_as_dev0(1, 1);
+ gpio_as_dev0(0, 0);
+ gpio_as_dev0(0, 1);
+ gpio_as_dev0(0, 2);
+ gpio_as_dev0(0, 3);
+ gpio_as_dev0(0, 4);
+ gpio_as_dev0(0, 5);
+ gpio_as_dev0(0, 6);
+ gpio_as_dev0(0, 7);
+
+ gpio_as_dev0(0, 16);
+ gpio_as_dev0(0, 17);
+ gpio_as_dev0(0, 26);
+
+ /* DM9000 interrupt is on GPIO E pin 19 */
+ gpio_as_intr_level(4, GPIO_DME_INT);
+ ih = evbmips_intr_establish(13, ingenic_dme_intr, sc);
+
+ if (ih == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt %d\n",
+ 13);
+ goto fail;
+ }
+
+ /*
+ * XXX grab MAC address set by uboot
+ * I'm not sure uboot will program the MAC address into the chip when
+ * not netbooting, so this needs to go away
+ */
+ dme_read_c(sc, DM9000_PAB0, enaddr, 6);
+ dme_attach(sc, enaddr);
+ return;
+fail:
+ if (ih) {
+ evbmips_intr_disestablish(ih);
+ }
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, 4);
+}
+
+static int
+ingenic_dme_intr(void *arg)
+{
+ uint32_t reg;
+ int ret = 0;
+
+ /* see if it's us */
+ reg = readreg(JZ_GPIO_E_BASE + JZ_GPIO_FLAG);
+ if (reg & GPIO_DME_INT_MASK) {
+ /* yes, it's ours, handle it... */
+ ret = dme_intr(arg);
+ /* ... and clear it */
+ writereg(JZ_GPIO_E_BASE + JZ_GPIO_FLAGC, GPIO_DME_INT_MASK);
+ }
+ return ret;
+}
Added: projects/ci20_mips/sys/mips/ingenic/ingenic_dwctwo.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/ingenic/ingenic_dwctwo.c Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,216 @@
+/* $NetBSD: ingenic_dwctwo.c,v 1.10 2015/04/28 15:07:07 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ingenic_dwctwo.c,v 1.10 2015/04/28 15:07:07 macallan Exp $");
+
+/*
+ * adapted from bcm2835_dwctwo.c
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/workqueue.h>
+
+#include <mips/ingenic/ingenic_var.h>
+#include <mips/ingenic/ingenic_regs.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+#include <dev/usb/usbdevs.h>
+
+#include <dwc2/dwc2var.h>
+#include <dwc2/dwc2.h>
+#include "dwc2_core.h"
+
+#include "opt_ingenic.h"
+
+struct ingenic_dwc2_softc {
+ struct dwc2_softc sc_dwc2;
+
+ void *sc_ih;
+};
+
+static struct dwc2_core_params ingenic_dwc2_params = {
+ .otg_cap = -1, /* HNP/SRP capable */
+ .otg_ver = -1, /* 1.3 */
+ .dma_enable = 1,
+ .dma_desc_enable = 0,
+ .speed = -1, /* High Speed */
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = 1024, /* 1024 DWORDs */
+ .host_nperio_tx_fifo_size = 1024, /* 1024 DWORDs */
+ .host_perio_tx_fifo_size = 1024, /* 1024 DWORDs */
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1, /* UTMI */
+ .phy_utmi_width = -1, /* 16 bits */
+ .phy_ulpi_ddr = -1, /* Single */
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1, /* 48 MHz */
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = -1,
+ .uframe_sched = 0,
+};
+
+static int ingenic_dwc2_match(device_t, struct cfdata *, void *);
+static void ingenic_dwc2_attach(device_t, device_t, void *);
+static void ingenic_dwc2_deferred(device_t);
+
+CFATTACH_DECL_NEW(ingenic_dwctwo, sizeof(struct ingenic_dwc2_softc),
+ ingenic_dwc2_match, ingenic_dwc2_attach, NULL, NULL);
+
+/* ARGSUSED */
+static int
+ingenic_dwc2_match(device_t parent, struct cfdata *match, void *aux)
+{
+ struct apbus_attach_args *aa = aux;
+
+ if (strcmp(aa->aa_name, "dwctwo") != 0)
+ return 0;
+
+ return 1;
+}
+
+/* ARGSUSED */
+static void
+ingenic_dwc2_attach(device_t parent, device_t self, void *aux)
+{
+ struct ingenic_dwc2_softc *sc = device_private(self);
+ struct apbus_attach_args *aa = aux;
+ uint32_t reg;
+ int error;
+
+ sc->sc_dwc2.sc_dev = self;
+
+ sc->sc_dwc2.sc_iot = aa->aa_bst;
+ sc->sc_dwc2.sc_bus.dmatag = aa->aa_dmat;
+ sc->sc_dwc2.sc_params = &ingenic_dwc2_params;
+
+ if (aa->aa_addr == 0)
+ aa->aa_addr = JZ_DWC2_BASE;
+
+ error = bus_space_map(aa->aa_bst, aa->aa_addr, 0x20000, 0,
+ &sc->sc_dwc2.sc_ioh);
+ if (error) {
+ aprint_error_dev(self,
+ "can't map registers for %s: %d\n", aa->aa_name, error);
+ return;
+ }
+
+ aprint_naive(": USB OTG controller\n");
+ aprint_normal(": USB OTG controller\n");
+
+ /* reset PHY, flash LED */
+ gpio_set(5, 15, 0);
+ delay(250000);
+ gpio_set(5, 15, 1);
+
+ reg = readreg(JZ_USBPCR);
+ reg |= PCR_VBUSVLDEXTSEL;
+ reg |= PCR_VBUSVLDEXT;
+ reg |= PCR_USB_MODE;
+ reg |= PCR_COMMONONN;
+ reg &= ~PCR_OTG_DISABLE;
+ writereg(JZ_USBPCR, reg);
+#ifdef INGENIC_DEBUG
+ printf("JZ_USBPCR %08x\n", reg);
+#endif
+
+ reg = readreg(JZ_USBPCR1);
+ reg |= PCR_SYNOPSYS;
+ reg |= PCR_REFCLK_CORE;
+ reg &= ~PCR_CLK_M;
+ reg |= PCR_CLK_48;
+ reg |= PCR_WORD_I_F0;
+ reg |= PCR_WORD_I_F1;
+ writereg(JZ_USBPCR1, reg);
+#ifdef INGENIC_DEBUG
+ printf("JZ_USBPCR1 %08x\n", reg);
+ printf("JZ_USBRDT %08x\n", readreg(JZ_USBRDT));
+#endif
+
+ delay(10000);
+
+ reg = readreg(JZ_USBPCR);
+ reg |= PCR_POR;
+ writereg(JZ_USBPCR, reg);
+ delay(1000);
+ reg &= ~PCR_POR;
+ writereg(JZ_USBPCR, reg);
+
+ delay(10000);
+
+ sc->sc_ih = evbmips_intr_establish(aa->aa_irq, dwc2_intr, &sc->sc_dwc2);
+
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt %d\n",
+ aa->aa_irq);
+ goto fail;
+ }
+
+ config_defer(self, ingenic_dwc2_deferred);
+
+ return;
+
+fail:
+ if (sc->sc_ih) {
+ evbmips_intr_disestablish(sc->sc_ih);
+ sc->sc_ih = NULL;
+ }
+ bus_space_unmap(sc->sc_dwc2.sc_iot, sc->sc_dwc2.sc_ioh, 0x20000);
+}
+
+static void
+ingenic_dwc2_deferred(device_t self)
+{
+ struct ingenic_dwc2_softc *sc = device_private(self);
+ int error;
+
+ sc->sc_dwc2.sc_id_vendor = USB_VENDOR_INGENIC;
+ strlcpy(sc->sc_dwc2.sc_vendor, "Ingenic", sizeof(sc->sc_dwc2.sc_vendor));
+ error = dwc2_init(&sc->sc_dwc2);
+ if (error != 0) {
+ aprint_error_dev(self, "couldn't initialize host, error=%d\n",
+ error);
+ return;
+ }
+ sc->sc_dwc2.sc_child = config_found(sc->sc_dwc2.sc_dev,
+ &sc->sc_dwc2.sc_bus, usbctlprint);
+}
Added: projects/ci20_mips/sys/mips/ingenic/ingenic_ehci.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/ci20_mips/sys/mips/ingenic/ingenic_ehci.c Sun May 17 16:14:48 2015 (r283030)
@@ -0,0 +1,155 @@
+/* $NetBSD: ingenic_ehci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2015 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ingenic_ehci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/workqueue.h>
+
+#include <mips/ingenic/ingenic_var.h>
+#include <mips/ingenic/ingenic_regs.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <dev/usb/ehcireg.h>
+#include <dev/usb/ehcivar.h>
+
+#include <dev/usb/usbdevs.h>
+
+#include "opt_ingenic.h"
+#include "ohci.h"
+
+static int ingenic_ehci_match(device_t, struct cfdata *, void *);
+static void ingenic_ehci_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(ingenic_ehci, sizeof(struct ehci_softc),
+ ingenic_ehci_match, ingenic_ehci_attach, NULL, NULL);
+
+#if NOHCI > 0
+extern device_t ingenic_ohci;
+#endif
+
+/* ARGSUSED */
+static int
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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