svn commit: r260360 - in projects/altix2/sys/ia64: ia64 sgisn

[Marcel Moolenaar]

Author: marcel
Date: Mon Jan  6 00:15:19 2014
New Revision: 260360
URL: http://svnweb.freebsd.org/changeset/base/260360

Log:
  Send PTC across the nodes. In its current form the Altix 450 keeps
  translation caches coherent across nodes but the Altix 350 gets in
  a wedge. More debugging is needed on the Altix 350.

Modified:
  projects/altix2/sys/ia64/ia64/pmap.c
  projects/altix2/sys/ia64/sgisn/sgisn_shub.c

Modified: projects/altix2/sys/ia64/ia64/pmap.c
==============================================================================
--- projects/altix2/sys/ia64/ia64/pmap.c	Sun Jan  5 23:45:53 2014	(r260359)
+++ projects/altix2/sys/ia64/ia64/pmap.c	Mon Jan  6 00:15:19 2014	(r260360)
@@ -108,6 +108,8 @@ __FBSDID("$FreeBSD$");
  * Region 7:	Direct-mapped cacheable
  */
 
+extern void shub_ptc(vm_offset_t, u_int);
+
 /* XXX move to a header. */
 extern uint64_t ia64_gateway_page[];
 
@@ -512,7 +514,7 @@ pmap_invalidate_page(vm_offset_t va)
 	struct ia64_lpte *pte;
 	struct pcpu *pc;
 	uint64_t tag;
-	u_int vhpt_ofs;
+	u_int rr, vhpt_ofs;
 
 	critical_enter();
 
@@ -529,6 +531,11 @@ pmap_invalidate_page(vm_offset_t va)
 	ia64_mf();
 	ia64_srlz_i();
 
+	rr = va >> 61;
+	if (rr < IA64_VM_MINKERN_REGION && PCPU_GET(md.current_pmap) != NULL)
+		rr = PCPU_GET(md.current_pmap)->pm_rid[rr];
+	shub_ptc(va, rr);
+
 	mtx_unlock_spin(&pmap_ptc_mutex);
 
 	ia64_invala();

Modified: projects/altix2/sys/ia64/sgisn/sgisn_shub.c
==============================================================================
--- projects/altix2/sys/ia64/sgisn/sgisn_shub.c	Sun Jan  5 23:45:53 2014	(r260359)
+++ projects/altix2/sys/ia64/sgisn/sgisn_shub.c	Mon Jan  6 00:15:19 2014	(r260360)
@@ -42,6 +42,7 @@ __FBSDID("$FreeBSD$");
 #include <vm/pmap.h>
 
 #include <machine/bus.h>
+#include <machine/cpu.h>
 #include <machine/md_var.h>
 #include <machine/resource.h>
 #include <machine/sal.h>
@@ -56,6 +57,7 @@ __FBSDID("$FreeBSD$");
 #include <ia64/sgisn/sgisn_shub.h>
 
 void shub_iack(const char *f, u_int xiv);
+void shub_ptc(vm_offset_t va, u_int rid);
 
 struct sgisn_shub_softc {
 	struct sgisn_fwhub *sc_fwhub;
@@ -606,3 +608,68 @@ shub_iack(const char *f, u_int xiv)
 
 	bus_space_write_8(sc->sc_tag, sc->sc_hndl, SHUB_MMR_EVENT_WR, ev);
 }
+
+void
+shub_ptc(vm_offset_t va, u_int rid)
+{
+	device_t dev;
+	struct sgisn_shub_softc *sc;
+	uint64_t cfg0, cfg1, ptc, ws, wsreg;
+	u_int mynas, nasid, shub1;
+
+	mynas = PCPU_GET(md.sgisn_nasid);
+	dev = devclass_get_device(sgisn_shub_devclass, mynas >> 1);
+	sc = (dev != NULL) ? device_get_softc(dev) : NULL;
+	if (sc == NULL)
+		return;
+	shub1 = (sc->sc_hubtype == 0) ? 1 : 0;
+
+	if (shub1) {
+		cfg0 = (1UL << 63) | ((uint64_t)rid << 8) |
+		    (PAGE_SHIFT << 2) | 1UL;
+		cfg1 = (1UL << 63) | IA64_RR_MASK(va);
+		ptc = 0;
+	} else {
+		cfg0 = cfg1 = 0;
+		ptc = (1UL << 63) | (va & 0x1ffffffffffff000UL) |
+		    (PAGE_SHIFT << 2) | 1UL;
+	}
+
+	nasid = 0;
+	while (1) {
+		if (nasid == mynas)
+			goto next;
+		dev = devclass_get_device(sgisn_shub_devclass, nasid >> 1);
+		sc = (dev != NULL) ? device_get_softc(dev) : NULL;
+		if (sc == NULL)
+			goto next;
+		if (shub1) {
+			bus_space_write_8(sc->sc_tag, sc->sc_hndl,
+			    SHUB_MMR_PTC_CFG0, cfg0);
+			bus_space_write_8(sc->sc_tag, sc->sc_hndl,
+			    SHUB_MMR_PTC_CFG1, cfg1);
+		} else
+			bus_space_write_8(sc->sc_tag, sc->sc_hndl,
+			    SHUB_MMR_PTC(rid), ptc);
+	 next:
+		nasid += 2;
+	}
+
+	/*
+	 * Wait for the writes to be complete.
+	 */
+	switch (PCPU_GET(md.sgisn_slice)) {
+	case 0:	wsreg = SHUB_MMR_PIO_WSTAT(0); break;
+	case 1:	wsreg = SHUB_MMR_PIO_WSTAT(2); break;
+	case 2:	wsreg = SHUB_MMR_PIO_WSTAT(1); break;
+	case 3:	wsreg = SHUB_MMR_PIO_WSTAT(3); break;
+	default:	return;
+	}
+	while (1) {
+		ws = bus_space_read_8(sc->sc_tag, sc->sc_hndl, wsreg);
+		KASSERT((ws & 2) == 0, ("%s: deadlock detected", __func__));
+		if ((ws >> 56) == ((shub1) ? 0x3f : 0))
+			return;
+		cpu_spinwait();
+	}
+}