svn commit: r257552 - projects/altix2/sys/ia64/sgisn
Marcel Moolenaar
marcel at FreeBSD.org
Sat Nov 2 18:40:19 UTC 2013
Author: marcel
Date: Sat Nov 2 18:40:18 2013
New Revision: 257552
URL: http://svnweb.freebsd.org/changeset/base/257552
Log:
The Altix 450 has 2 TIOCP bridge ASICs and one PPB bridge ASIC. The
Altix 350 has only PIC ASICs. Extend the existing driver to handle
the TIOCP ASIC as well, given that the registers we know of are the
same between them. Don't probe the PPB for now -- I have no data on
it at all. To this end:
1. Check the ASIC type in the probe function to match what we know.
2. Rename constants using s/PIC_/PCIB_/g.
Note that with this change we still get a machine check. It looks
like the first read to the memory mapped I/O is causing it, which
so far seems to indicate that we don't have the right address yet.
Bit 0 of the NASID is 1 for the TIOCP, so it's wired differently
from the PIC -- even though the S/W interface seems identical.
Figuring this out is going to be "interesting".
Modified:
projects/altix2/sys/ia64/sgisn/sgisn_pcib.c
projects/altix2/sys/ia64/sgisn/sgisn_pcib.h
Modified: projects/altix2/sys/ia64/sgisn/sgisn_pcib.c
==============================================================================
--- projects/altix2/sys/ia64/sgisn/sgisn_pcib.c Sat Nov 2 18:33:14 2013 (r257551)
+++ projects/altix2/sys/ia64/sgisn/sgisn_pcib.c Sat Nov 2 18:40:18 2013 (r257552)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Marcel Moolenaar
+ * Copyright (c) 2010-2013 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -77,7 +77,7 @@ struct sgisn_pcib_softc {
struct rman sc_iomem;
uint32_t *sc_flush_intr[PCI_SLOTMAX + 1];
uint64_t *sc_flush_addr[PCI_SLOTMAX + 1];
- uint64_t sc_ate[PIC_REG_ATE_SIZE / 64];
+ uint64_t sc_ate[PCIB_REG_ATE_SIZE / 64];
struct mtx sc_ate_mtx;
};
@@ -377,7 +377,7 @@ sgisn_pcib_setup_intr(device_t dev, devi
// rman_get_start(irq), flags, ifltr, ihdlr, arg, cookiep);
sc = device_get_softc(dev);
- ie = bus_space_read_8(sc->sc_tag, sc->sc_hndl, PIC_REG_INT_ENABLE);
+ ie = bus_space_read_8(sc->sc_tag, sc->sc_hndl, PCIB_REG_INT_ENABLE);
// device_printf(dev, "INT_ENABLE=%#lx\n", ie);
error = bus_generic_setup_intr(dev, child, irq, flags, ifltr, ihdlr,
@@ -388,8 +388,12 @@ sgisn_pcib_setup_intr(device_t dev, devi
static int
sgisn_pcib_probe(device_t dev)
{
+ struct ia64_sal_result r;
+ struct sgisn_fwpcib *fwbus;
device_t parent;
uintptr_t bus, seg;
+ u_long addr;
+ int res;
parent = device_get_parent(dev);
if (parent == NULL)
@@ -399,8 +403,22 @@ sgisn_pcib_probe(device_t dev)
BUS_READ_IVAR(parent, dev, SHUB_IVAR_PCIBUS, &bus))
return (ENXIO);
- device_set_desc(dev, "SGI PCI-X host controller");
- return (BUS_PROBE_DEFAULT);
+ r = ia64_sal_entry(SAL_SGISN_IOBUS_INFO, seg, bus,
+ ia64_tpa((uintptr_t)&addr), 0, 0, 0, 0);
+ if (r.sal_status != 0 || addr == 0)
+ return (ENXIO);
+ fwbus = (void *)IA64_PHYS_TO_RR7(addr);
+ switch (fwbus->fw_common.bus_asic) {
+ case SGISN_PCIB_PIC:
+ case SGISN_PCIB_TIOCP:
+ device_set_desc(dev, "SGI PCI/PCI-X host controller");
+ res = BUS_PROBE_DEFAULT;
+ break;
+ default:
+ res = ENXIO;
+ break;
+ }
+ return (res);
}
static int
@@ -463,7 +481,7 @@ sgisn_pcib_attach(device_t dev)
sc->sc_fwbus = (void *)IA64_PHYS_TO_RR7(addr);
sc->sc_ioaddr = IA64_RR_MASK(sc->sc_fwbus->fw_common.bus_base);
sc->sc_tag = IA64_BUS_SPACE_MEM;
- bus_space_map(sc->sc_tag, sc->sc_ioaddr, PIC_REG_SIZE, 0,
+ bus_space_map(sc->sc_tag, sc->sc_ioaddr, PCIB_REG_SIZE, 0,
&sc->sc_hndl);
if (bootverbose)
@@ -473,13 +491,13 @@ sgisn_pcib_attach(device_t dev)
sc->sc_fwbus->fw_type, sc->sc_fwbus->fw_mode);
/* Set the preferred I/O MMU page size -- 4KB or 16KB. */
- ctrl = bus_space_read_8(sc->sc_tag, sc->sc_hndl, PIC_REG_WGT_CTRL);
+ ctrl = bus_space_read_8(sc->sc_tag, sc->sc_hndl, PCIB_REG_WGT_CTRL);
#if SGISN_PCIB_PAGE_SHIFT == 12
ctrl &= ~(1UL << 21);
#else
ctrl |= 1UL << 21;
#endif
- bus_space_write_8(sc->sc_tag, sc->sc_hndl, PIC_REG_WGT_CTRL, ctrl);
+ bus_space_write_8(sc->sc_tag, sc->sc_hndl, PCIB_REG_WGT_CTRL, ctrl);
mtx_init(&sc->sc_ate_mtx, device_get_nameunit(dev), NULL, MTX_SPIN);
@@ -620,7 +638,7 @@ sgisn_pcib_iommu_map(device_t bus, devic
ate = 0;
entry = ~0;
- while (ate < (PIC_REG_ATE_SIZE / 64) && entry == ~0) {
+ while (ate < (PCIB_REG_ATE_SIZE / 64) && entry == ~0) {
bits = sc->sc_ate[ate];
/* Move to the next long if this one is full. */
if (bits == ~0UL) {
@@ -657,7 +675,7 @@ sgisn_pcib_iommu_map(device_t bus, devic
ate++;
}
if (entry != ~0) {
- KASSERT(ate < (PIC_REG_ATE_SIZE / 64), ("foo: ate"));
+ KASSERT(ate < (PCIB_REG_ATE_SIZE / 64), ("foo: ate"));
KASSERT(bitshft <= (64 - count), ("foo: bitshft"));
KASSERT(entry == (ate * 64 + bitshft), ("foo: math"));
bits = (count < 64) ? ((1UL << count) - 1UL) << bitshft : ~0UL;
@@ -682,7 +700,7 @@ sgisn_pcib_iommu_map(device_t bus, devic
ba |= (u_long)sc->sc_fwbus->fw_hub_xid << 8;
while (count > 0) {
bus_space_write_8(sc->sc_tag, sc->sc_hndl,
- PIC_REG_ATE(entry), ba);
+ PCIB_REG_ATE(entry), ba);
ba += SGISN_PCIB_PAGE_SIZE;
entry++;
count--;
@@ -712,7 +730,7 @@ sgisn_pcib_iommu_unmap(device_t bus, dev
entry = (ba >> SGISN_PCIB_PAGE_SHIFT);
KASSERT(count <= 64, ("foo: count"));
- KASSERT((entry + count) <= PIC_REG_ATE_SIZE, ("foo"));
+ KASSERT((entry + count) <= PCIB_REG_ATE_SIZE, ("foo"));
bitshft = entry & 64;
KASSERT(bitshft <= (64 - count), ("foo: bitshft"));
bits = (count < 64) ? ((1UL << count) - 1UL) << bitshft : ~0UL;
@@ -720,7 +738,7 @@ sgisn_pcib_iommu_unmap(device_t bus, dev
while (count > 0) {
bus_space_write_8(sc->sc_tag, sc->sc_hndl,
- PIC_REG_ATE(entry), 0);
+ PCIB_REG_ATE(entry), 0);
entry++;
count--;
}
Modified: projects/altix2/sys/ia64/sgisn/sgisn_pcib.h
==============================================================================
--- projects/altix2/sys/ia64/sgisn/sgisn_pcib.h Sat Nov 2 18:33:14 2013 (r257551)
+++ projects/altix2/sys/ia64/sgisn/sgisn_pcib.h Sat Nov 2 18:40:18 2013 (r257552)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Marcel Moolenaar
+ * Copyright (c) 2011-2013 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,52 +29,56 @@
#ifndef _IA64_SGISN_PCIB_H_
#define _IA64_SGISN_PCIB_H_
-#define PIC_REG_SIZE (512 * 1024)
+/* Supported ASIC types. */
+#define SGISN_PCIB_PIC 2
+#define SGISN_PCIB_TIOCP 3
+
+#define PCIB_REG_SIZE (512 * 1024)
+
+#define PCIB_REG_WGT_ID 0x00000
+#define PCIB_REG_WGT_STAT 0x00008
+#define PCIB_REG_WGT_ERR_H 0x00010
+#define PCIB_REG_WGT_ERR 0x00018
+#define PCIB_REG_WGT_CTRL 0x00020
+#define PCIB_REG_WGT_REQ_TOUT 0x00028
+#define PCIB_REG_WGT_INT_H 0x00030
+#define PCIB_REG_WGT_INT 0x00038
+#define PCIB_REG_WGT_ERRCMD 0x00040
+#define PCIB_REG_WGT_LLP 0x00048
+#define PCIB_REG_WGT_TFLUSH 0x00050
+#define PCIB_REG_WGT_AUX_ERR 0x00058
+#define PCIB_REG_WGT_RSP_H 0x00060
+#define PCIB_REG_WGT_RSP 0x00068
+#define PCIB_REG_WGT_TSTPIN_CTL 0x00070
+#define PCIB_REG_WGT_ADDR_LKERR 0x00078
+
+#define PCIB_REG_DIR_MAP 0x00080
+#define PCIB_REG_MAP_FAULT 0x00090
+#define PCIB_REG_ARBITRATION 0x000a0
+#define PCIB_REG_ATE_PARERR 0x000b0
+#define PCIB_REG_BUS_TOUT 0x000c0
+#define PCIB_REG_PCI_CFG 0x000c8
+#define PCIB_REG_PCI_ERR_H 0x000d0
+#define PCIB_REG_PCI_ERR 0x000d8
+
+#define PCIB_REG_INT_STATUS 0x00100
+#define PCIB_REG_INT_ENABLE 0x00108
+#define PCIB_REG_INT_RSTSTAT 0x00110
+#define PCIB_REG_INT_MODE 0x00118
+#define PCIB_REG_INT_DEVICE 0x00120
+#define PCIB_REG_INT_HOSTERR 0x00128
+#define PCIB_REG_INT_ADDR(x) (0x00130 + ((x) << 3))
+#define PCIB_REG_INT_ERRVIEW 0x00170
+#define PCIB_REG_INT_MULTI 0x00178
+#define PCIB_REG_INT_FORCE(x) (0x00180 + ((x) << 3))
+#define PCIB_REG_INT_PIN(x) (0x001c0 + ((x) << 3))
+
+#define PCIB_REG_DEVICE(x) (0x00200 + ((x) << 3))
+#define PCIB_REG_WR_REQ(x) (0x00240 + ((x) << 3))
+#define PCIB_REG_RRB_MAP(x) (0x00280 + ((x) << 3))
-#define PIC_REG_WGT_ID 0x00000
-#define PIC_REG_WGT_STAT 0x00008
-#define PIC_REG_WGT_ERR_H 0x00010
-#define PIC_REG_WGT_ERR 0x00018
-#define PIC_REG_WGT_CTRL 0x00020
-#define PIC_REG_WGT_REQ_TOUT 0x00028
-#define PIC_REG_WGT_INT_H 0x00030
-#define PIC_REG_WGT_INT 0x00038
-#define PIC_REG_WGT_ERRCMD 0x00040
-#define PIC_REG_WGT_LLP 0x00048
-#define PIC_REG_WGT_TFLUSH 0x00050
-#define PIC_REG_WGT_AUX_ERR 0x00058
-#define PIC_REG_WGT_RSP_H 0x00060
-#define PIC_REG_WGT_RSP 0x00068
-#define PIC_REG_WGT_TSTPIN_CTL 0x00070
-#define PIC_REG_WGT_ADDR_LKERR 0x00078
-
-#define PIC_REG_DIR_MAP 0x00080
-#define PIC_REG_MAP_FAULT 0x00090
-#define PIC_REG_ARBITRATION 0x000a0
-#define PIC_REG_ATE_PARERR 0x000b0
-#define PIC_REG_BUS_TOUT 0x000c0
-#define PIC_REG_PCI_CFG 0x000c8
-#define PIC_REG_PCI_ERR_H 0x000d0
-#define PIC_REG_PCI_ERR 0x000d8
-
-#define PIC_REG_INT_STATUS 0x00100
-#define PIC_REG_INT_ENABLE 0x00108
-#define PIC_REG_INT_RSTSTAT 0x00110
-#define PIC_REG_INT_MODE 0x00118
-#define PIC_REG_INT_DEVICE 0x00120
-#define PIC_REG_INT_HOSTERR 0x00128
-#define PIC_REG_INT_ADDR(x) (0x00130 + ((x) << 3))
-#define PIC_REG_INT_ERRVIEW 0x00170
-#define PIC_REG_INT_MULTI 0x00178
-#define PIC_REG_INT_FORCE(x) (0x00180 + ((x) << 3))
-#define PIC_REG_INT_PIN(x) (0x001c0 + ((x) << 3))
-
-#define PIC_REG_DEVICE(x) (0x00200 + ((x) << 3))
-#define PIC_REG_WR_REQ(x) (0x00240 + ((x) << 3))
-#define PIC_REG_RRB_MAP(x) (0x00280 + ((x) << 3))
-
-#define PIC_REG_ATE(x) (0x10000 + ((x) << 3))
-#define PIC_REG_ATE_SIZE 1024
+#define PCIB_REG_ATE(x) (0x10000 + ((x) << 3))
+#define PCIB_REG_ATE_SIZE 1024
struct sgisn_fwpcib {
struct sgisn_fwbus fw_common;
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