svn commit: r242758 - projects/efika_mx/sys/arm/freescale/imx
Aleksandr Rybalko
ray at FreeBSD.org
Thu Nov 8 12:45:36 UTC 2012
Author: ray
Date: Thu Nov 8 12:45:35 2012
New Revision: 242758
URL: http://svnweb.freebsd.org/changeset/base/242758
Log:
Clock Controller Module driver.
Obtained from: NetBSD
Added:
projects/efika_mx/sys/arm/freescale/imx/imx51_ccm.c
projects/efika_mx/sys/arm/freescale/imx/imx51_ccmreg.h
projects/efika_mx/sys/arm/freescale/imx/imx51_ccmvar.h
projects/efika_mx/sys/arm/freescale/imx/imx51_dpllreg.h
Added: projects/efika_mx/sys/arm/freescale/imx/imx51_ccm.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/efika_mx/sys/arm/freescale/imx/imx51_ccm.c Thu Nov 8 12:45:35 2012 (r242758)
@@ -0,0 +1,472 @@
+/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Oleksandr Rybalko
+ * under sponsorship from the FreeBSD Foundation.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Clock Controller Module (CCM)
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include <arm/freescale/imx/imx51_ccmvar.h>
+#include <arm/freescale/imx/imx51_ccmreg.h>
+#include <arm/freescale/imx/imx51_dpllreg.h>
+
+#define IMXCCMDEBUG
+#undef IMXCCMDEBUG
+
+#ifndef IMX51_OSC_FREQ
+#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
+#endif
+
+#ifndef IMX51_CKIL_FREQ
+#define IMX51_CKIL_FREQ 32768
+#endif
+
+struct imxccm_softc {
+ device_t sc_dev;
+ struct resource *res[7];
+ u_int64_t pll_freq[IMX51_N_DPLLS];
+};
+
+struct imxccm_softc *ccm_softc = NULL;
+
+static uint64_t imx51_get_pll_freq(u_int);
+
+static int imxccm_match(device_t);
+static int imxccm_attach(device_t);
+
+static device_method_t imxccm_methods[] = {
+ DEVMETHOD(device_probe, imxccm_match),
+ DEVMETHOD(device_attach, imxccm_attach),
+
+ DEVMETHOD_END
+};
+
+static driver_t imxccm_driver = {
+ "imxccm",
+ imxccm_methods,
+ sizeof(struct imxccm_softc),
+};
+
+static devclass_t imxccm_devclass;
+
+DRIVER_MODULE(imxccm, simplebus, imxccm_driver, imxccm_devclass, 0, 0);
+
+static struct resource_spec imxccm_spec[] = {
+ { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */
+ { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* DPLLIP1 */
+ { SYS_RES_MEMORY, 2, RF_ACTIVE }, /* DPLLIP2 */
+ { SYS_RES_MEMORY, 3, RF_ACTIVE }, /* DPLLIP3 */
+ { SYS_RES_IRQ, 0, RF_ACTIVE }, /* 71 */
+ { SYS_RES_IRQ, 1, RF_ACTIVE }, /* 72 */
+ { -1, 0 }
+};
+
+static int
+imxccm_match(device_t dev)
+{
+
+ if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm"))
+ return (ENXIO);
+
+ device_set_desc(dev, "Freescale Clock Control Module");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+imxccm_attach(device_t dev)
+{
+ struct imxccm_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+
+ if (bus_alloc_resources(dev, imxccm_spec, sc->res)) {
+ device_printf(dev, "could not allocate resources\n");
+ return (ENXIO);
+ }
+
+ ccm_softc = sc;
+
+ imx51_get_pll_freq(1);
+ imx51_get_pll_freq(2);
+ imx51_get_pll_freq(3);
+
+ device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n",
+ sc->pll_freq[0] / 1000000,
+ sc->pll_freq[1] / 1000000,
+ sc->pll_freq[2] / 1000000);
+ device_printf(dev, "CPU clock=%d, UART clock=%d\n",
+ imx51_get_clock(IMX51CLK_ARM_ROOT),
+ imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
+ device_printf(dev,
+ "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
+ imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
+ imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
+ imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
+ imx51_get_clock(IMX51CLK_PERCLK_ROOT));
+
+
+ return (0);
+}
+
+u_int
+imx51_get_clock(enum imx51_clock clk)
+{
+ u_int freq;
+ u_int sel;
+ uint32_t cacrr; /* ARM clock root register */
+ uint32_t ccsr;
+ uint32_t cscdr1;
+ uint32_t cscmr1;
+ uint32_t cbcdr;
+ uint32_t cbcmr;
+ uint32_t cdcr;
+
+ if (ccm_softc == NULL)
+ return (0);
+
+ switch (clk) {
+ case IMX51CLK_PLL1:
+ case IMX51CLK_PLL2:
+ case IMX51CLK_PLL3:
+ return ccm_softc->pll_freq[clk-IMX51CLK_PLL1];
+ case IMX51CLK_PLL1SW:
+ ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR);
+ if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
+ return ccm_softc->pll_freq[1-1];
+ /* step clock */
+ /* FALLTHROUGH */
+ case IMX51CLK_PLL1STEP:
+ ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR);
+ switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
+ case 0:
+ return imx51_get_clock(IMX51CLK_LP_APM);
+ case 1:
+ return 0; /* XXX PLL bypass clock */
+ case 2:
+ return ccm_softc->pll_freq[2-1] /
+ (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
+ CCSR_PLL2_DIV_PODF_SHIFT));
+ case 3:
+ return ccm_softc->pll_freq[3-1] /
+ (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
+ CCSR_PLL3_DIV_PODF_SHIFT));
+ }
+ /*NOTREACHED*/
+ case IMX51CLK_PLL2SW:
+ ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR);
+ if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0)
+ return imx51_get_clock(IMX51CLK_PLL2);
+ return 0; /* XXX PLL2 bypass clk */
+ case IMX51CLK_PLL3SW:
+ ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR);
+ if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0)
+ return imx51_get_clock(IMX51CLK_PLL3);
+ return 0; /* XXX PLL3 bypass clk */
+
+ case IMX51CLK_LP_APM:
+ ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR);
+ return (ccsr & CCSR_LP_APM) ?
+ imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ;
+
+ case IMX51CLK_ARM_ROOT:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ cacrr = bus_read_4(ccm_softc->res[0], CCMC_CACRR);
+ return freq / (cacrr + 1);
+
+ /* ... */
+ case IMX51CLK_MAIN_BUS_CLK_SRC:
+ cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR);
+ if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
+ freq = imx51_get_clock(IMX51CLK_PLL2SW);
+ else {
+ freq = 0;
+ cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR);
+ switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
+ CBCMR_PERIPH_APM_SEL_SHIFT) {
+ case 0:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ break;
+ case 1:
+ freq = imx51_get_clock(IMX51CLK_PLL3SW);
+ break;
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ case 3:
+ /* XXX: error */
+ break;
+ }
+ }
+ return freq;
+ case IMX51CLK_MAIN_BUS_CLK:
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+ cdcr = bus_read_4(ccm_softc->res[0], CCMC_CDCR);
+ return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
+ CDCR_PERIPH_CLK_DVFS_PODF_SHIFT;
+ case IMX51CLK_AHB_CLK_ROOT:
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
+ cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR);
+ return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
+ CBCDR_AHB_PODF_SHIFT));
+ case IMX51CLK_IPG_CLK_ROOT:
+ freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+ cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR);
+ return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
+ CBCDR_IPG_PODF_SHIFT));
+
+ case IMX51CLK_PERCLK_ROOT:
+ cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR);
+ if (cbcmr & CBCMR_PERCLK_IPG_SEL)
+ return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
+ if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ else
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+ cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR);
+
+#ifdef IMXCCMDEBUG
+ printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
+#endif
+
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
+ CBCDR_PERCLK_PRED1_SHIFT);
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
+ CBCDR_PERCLK_PRED2_SHIFT);
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
+ CBCDR_PERCLK_PODF_SHIFT);
+ return freq;
+ case IMX51CLK_UART_CLK_ROOT:
+ cscdr1 = bus_read_4(ccm_softc->res[0], CCMC_CSCDR1);
+ cscmr1 = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1);
+
+#ifdef IMXCCMDEBUG
+ printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
+#endif
+
+ sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >>
+ CSCMR1_UART_CLK_SEL_SHIFT;
+
+ freq = 0; /* shut up GCC */
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ }
+
+ return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >>
+ CSCDR1_UART_CLK_PRED_SHIFT)) /
+ (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >>
+ CSCDR1_UART_CLK_PODF_SHIFT));
+ case IMX51CLK_IPU_HSP_CLK_ROOT:
+ freq = 0;
+ cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR);
+ switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >>
+ CBCMR_IPU_HSP_CLK_SEL_SHIFT) {
+ case 0:
+ freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
+ break;
+ case 1:
+ freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK);
+ break;
+ case 2:
+ freq = imx51_get_clock(
+ IMX51CLK_EMI_SLOW_CLK_ROOT);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+ break;
+ }
+ return freq;
+ default:
+ device_printf(ccm_softc->sc_dev,
+ "clock %d: not supported yet\n", clk);
+ return 0;
+ }
+}
+
+
+static uint64_t
+imx51_get_pll_freq(u_int pll_no)
+{
+ uint32_t dp_ctrl;
+ uint32_t dp_op;
+ uint32_t dp_mfd;
+ uint32_t dp_mfn;
+ uint32_t mfi;
+ int32_t mfn;
+ uint32_t mfd;
+ uint32_t pdf;
+ uint32_t ccr;
+ uint64_t freq = 0;
+ u_int ref = 0;
+
+ KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id"));
+
+ dp_ctrl = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_CTL);
+
+ if (dp_ctrl & DP_CTL_HFSM) {
+ dp_op = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_HFS_OP);
+ dp_mfd = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_HFS_MFD);
+ dp_mfn = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_HFS_MFN);
+ } else {
+ dp_op = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_OP);
+ dp_mfd = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_MFD);
+ dp_mfn = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_MFN);
+ }
+
+ pdf = dp_op & DP_OP_PDF_MASK;
+ mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT);
+ mfd = dp_mfd;
+ if (dp_mfn & 0x04000000)
+ /* 27bit signed value */
+ mfn = (uint32_t)(0xf8000000 | dp_mfn);
+ else
+ mfn = dp_mfn;
+
+ switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) {
+ case DP_CTL_REF_CLK_SEL_COSC:
+ /* Internal Oscillator */
+ /* TODO: get from FDT "fsl,imx-osc" */
+ ref = 24000000; /* IMX51_OSC_FREQ */
+ break;
+ case DP_CTL_REF_CLK_SEL_FPM:
+ ccr = bus_read_4(ccm_softc->res[0], CCMC_CCR);
+ if (ccr & CCR_FPM_MULT)
+ /* TODO: get from FDT "fsl,imx-ckil" */
+ ref = 32768 * 1024;
+ else
+ /* TODO: get from FDT "fsl,imx-ckil" */
+ ref = 32768 * 512;
+ break;
+ default:
+ ref = 0;
+ }
+
+ if (dp_ctrl & DP_CTL_REF_CLK_DIV)
+ ref /= 2;
+
+ ref *= 4;
+ freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1);
+ freq /= pdf + 1;
+
+ if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN))
+ freq /= 2;
+
+#ifdef IMXCCMDEBUG
+ printf("ref: %dKHz ", ref);
+ printf("dp_ctl: %08x ", dp_ctrl);
+ printf("pdf: %3d ", pdf);
+ printf("mfi: %3d ", mfi);
+ printf("mfd: %3d ", mfd);
+ printf("mfn: %3d ", mfn);
+ printf("pll: %d\n", (uint32_t)freq);
+#endif
+
+ ccm_softc->pll_freq[pll_no-1] = freq;
+
+ return (freq);
+}
+
+void
+imx51_clk_gating(int clk_src, int mode)
+{
+ int field, group;
+ uint32_t reg;
+
+ group = CCMR_CCGR_MODULE(clk_src);
+ field = clk_src % CCMR_CCGR_NSOURCE;
+ reg = bus_read_4(ccm_softc->res[0], CCMC_CCGR(group));
+ reg &= ~(0x03 << field * 2);
+ reg |= (mode << field * 2);
+ bus_write_4(ccm_softc->res[0], CCMC_CCGR(group), reg);
+}
+
+int
+imx51_get_clk_gating(int clk_src)
+{
+ uint32_t reg;
+
+ reg = bus_read_4(ccm_softc->res[0],
+ CCMC_CCGR(CCMR_CCGR_MODULE(clk_src)));
+ return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03);
+}
+
Added: projects/efika_mx/sys/arm/freescale/imx/imx51_ccmreg.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/efika_mx/sys/arm/freescale/imx/imx51_ccmreg.h Thu Nov 8 12:45:35 2012 (r242758)
@@ -0,0 +1,249 @@
+/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Oleksandr Rybalko
+ * under sponsorship from the FreeBSD Foundation.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _IMX51_CCMREG_H
+#define _IMX51_CCMREG_H
+
+#include <sys/cdefs.h>
+
+/* register offset address */
+
+#define CCMC_BASE 0x73fd4000
+#define CCMC_CCR 0x0000
+#define CCR_FPM_MULT 0x00001000
+#define CCMC_CCDR 0x0004
+#define CCMC_CSR 0x0008
+#define CCMC_CCSR 0x000c
+#define CCSR_LP_APM 0x00000200
+#define CCSR_STEP_SEL_SHIFT 7
+#define CCSR_STEP_SEL_MASK 0x00000180
+#define CCSR_PLL2_DIV_PODF_SHIFT 5
+#define CCSR_PLL2_DIV_PODF_MASK 0x00000060
+#define CCSR_PLL3_DIV_PODF_SHIFT 3
+#define CCSR_PLL3_DIV_PODF_MASK 0x00000030
+#define CCSR_PLL1_SW_CLK_SEL 0x00000004
+#define CCSR_PLL2_SW_CLK_SEL 0x00000002
+#define CCSR_PLL3_SW_CLK_SEL 0x00000001
+#define CCMC_CACRR 0x0010
+#define CCMC_CBCDR 0x0014
+#define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000
+#define CBCDR_DDR_CLK_PODF_SHIFT 27
+#define CBCDR_DDR_CLK_PODF_MASK 0x38000000
+#define CBCDR_EMI_CLK_SEL 0x04000000
+#define CBCDR_PERIPH_CLK_SEL 0x02000000
+#define CBCDR_EMI_SLOW_PODF_SHIFT 22
+#define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000
+#define CBCDR_AXI_B_PODF_SHIFT 19
+#define CBCDR_AXI_B_PODF_MASK 0x00380000
+#define CBCDR_AXI_A_PODF_SHIFT 16
+#define CBCDR_AXI_A_PODF_MASK 0x1fff0000
+#define CBCDR_NFC_PODF_SHIFT 13
+#define CBCDR_NFC_PODF_MASK 0x00018000
+#define CBCDR_AHB_PODF_SHIFT 10
+#define CBCDR_AHB_PODF_MASK 0x00001c00
+#define CBCDR_IPG_PODF_SHIFT 8
+#define CBCDR_IPG_PODF_MASK 0x00000300
+#define CBCDR_PERCLK_PRED1_SHIFT 6
+#define CBCDR_PERCLK_PRED1_MASK 0x000000c0
+#define CBCDR_PERCLK_PRED2_SHIFT 3
+#define CBCDR_PERCLK_PRED2_MASK 0x00000038
+#define CBCDR_PERCLK_PODF_SHIFT 0
+#define CBCDR_PERCLK_PODF_MASK 0x00000007
+#define CCMC_CBCMR 0x0018
+#define CBCMR_PERIPH_APM_SEL_SHIFT 12
+#define CBCMR_PERIPH_APM_SEL_MASK 0x00003000
+#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6
+#define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0
+#define CBCMR_PERCLK_LP_APM_SEL 0x00000002
+#define CBCMR_PERCLK_IPG_SEL 0x00000001
+#define CCMC_CSCMR1 0x001c
+#define CSCMR1_UART_CLK_SEL_SHIFT 24
+#define CSCMR1_UART_CLK_SEL_MASK 0x03000000
+#define CCMC_CSCMR2 0x0020
+#define CCMC_CSCDR1 0x0024
+#define CSCDR1_UART_CLK_PRED_SHIFT 3
+#define CSCDR1_UART_CLK_PRED_MASK 0x00000038
+#define CSCDR1_UART_CLK_PODF_SHIFT 0
+#define CSCDR1_UART_CLK_PODF_MASK 0x00000007
+#define CCMC_CS1CDR 0x0028
+#define CCMC_CS2CDR 0x002c
+#define CCMC_CDCDR 0x0030
+#define CCMC_CSCDR2 0x0038
+#define CCMC_CSCDR3 0x003c
+#define CCMC_CSCDR4 0x0040
+#define CCMC_CWDR 0x0044
+#define CCMC_CDHIPR 0x0048
+#define CCMC_CDCR 0x004c
+#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0
+#define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003
+#define CCMC_CTOR 0x0050
+#define CCMC_CLPCR 0x0054
+#define CCMC_CISR 0x0058
+#define CCMC_CIMR 0x005c
+#define CCMC_CCOSR 0x0060
+#define CCMC_CGPR 0x0064
+#define CCMC_CCGR(n) (0x0068 + (n) * 4)
+#define CCMC_CMEOR 0x0084
+
+#define CCMC_SIZE 0x88
+
+/* CCGR Clock Gate Register */
+
+#define CCMR_CCGR_NSOURCE 16
+#define CCMR_CCGR_NGROUPS 7
+#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE)
+#define __CCGR_NUM(a, b) ((a) * 16 + (b))
+
+#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0)
+#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1)
+#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2)
+#define CCGR_TZIC_CLK __CCGR_NUM(0, 3)
+#define CCGR_DAP_CLK __CCGR_NUM(0, 4)
+#define CCGR_TPIU_CLK __CCGR_NUM(0, 5)
+#define CCGR_CTI2_CLK __CCGR_NUM(0, 6)
+#define CCGR_CTI3_CLK __CCGR_NUM(0, 7)
+#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8)
+#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9)
+#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10)
+#define CCGR_ROM_CLK __CCGR_NUM(0, 11)
+#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12)
+#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13)
+#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14)
+#define CCGR_IIM_CLK __CCGR_NUM(0, 15)
+#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0)
+#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1)
+#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2)
+#define CCGR_UART1_CLK __CCGR_NUM(1, 3)
+#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4)
+#define CCGR_UART2_CLK __CCGR_NUM(1, 5)
+#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6)
+#define CCGR_UART3_CLK __CCGR_NUM(1, 7)
+#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8)
+#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9)
+#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10)
+#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11)
+#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12)
+#define CCGR_FIRI_CLK __CCGR_NUM(1, 13)
+#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14)
+#define CCGR_SCC_CLK __CCGR_NUM(1, 15)
+
+#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0)
+#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1)
+#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2)
+#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3)
+#define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4)
+#define CCGR_PWM1_CLK __CCGR_NUM(2, 5)
+#define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6)
+#define CCGR_PWM2_CLK __CCGR_NUM(2, 7)
+#define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8)
+#define CCGR_GPT_CLK __CCGR_NUM(2, 9)
+#define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10)
+#define CCGR_OWIRE_CLK __CCGR_NUM(2, 11)
+#define CCGR_FEC_CLK __CCGR_NUM(2, 12)
+#define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13)
+#define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14)
+#define CCGR_TVE_CLK __CCGR_NUM(2, 15)
+
+#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0)
+#define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1)
+#define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2)
+#define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3)
+#define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4)
+#define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5)
+#define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6)
+#define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7)
+#define CCGR_SSI1_CLK __CCGR_NUM(3, 8)
+#define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9)
+#define CCGR_SSI2_CLK __CCGR_NUM(3, 10)
+#define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11)
+#define CCGR_SSI3_CLK __CCGR_NUM(3, 12)
+#define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13)
+#define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14)
+#define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15)
+
+#define CCGR_PATA_CLK __CCGR_NUM(4, 0)
+#define CCGR_SIM_CLK __CCGR_NUM(4, 1)
+#define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2)
+#define CCGR_SAHARA_CLK __CCGR_NUM(4, 3)
+#define CCGR_RTIC_CLK __CCGR_NUM(4, 4)
+#define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5)
+#define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6)
+#define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7)
+#define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8)
+#define CCGR_CSPI_CLK __CCGR_NUM(4, 9)
+#define CCGR_SRTC_CLK __CCGR_NUM(4, 10)
+#define CCGR_SDMA_CLK __CCGR_NUM(4, 11)
+
+#define CCGR_SPBA_CLK __CCGR_NUM(5, 0)
+#define CCGR_GPU_CLK __CCGR_NUM(5, 1)
+#define CCGR_GARB_CLK __CCGR_NUM(5, 2)
+#define CCGR_VPU_CLK __CCGR_NUM(5, 3)
+#define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4)
+#define CCGR_IPU_CLK __CCGR_NUM(5, 5)
+#define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0)
+#define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1)
+#define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2)
+#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3)
+#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4)
+#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5)
+
+#define CCGR_CLK_MODE_OFF 0
+#define CCGR_CLK_MODE_RUNMODE 1
+#define CCGR_CLK_MODE_ALWAYS 3
+
+#endif /* _IMX51_CCMREG_H */
+
Added: projects/efika_mx/sys/arm/freescale/imx/imx51_ccmvar.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/efika_mx/sys/arm/freescale/imx/imx51_ccmvar.h Thu Nov 8 12:45:35 2012 (r242758)
@@ -0,0 +1,109 @@
+/* $NetBSD: imx51_ccmvar.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Oleksandr Rybalko
+ * under sponsorship from the FreeBSD Foundation.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _ARM_IMX_IMX51_CCMVAR_H_
+#define _ARM_IMX_IMX51_CCMVAR_H_
+
+enum imx51_clock {
+ IMX51CLK_FPM,
+ IMX51CLK_PLL1,
+ IMX51CLK_PLL2,
+ IMX51CLK_PLL3,
+ IMX51CLK_PLL1SW,
+ IMX51CLK_PLL2SW,
+ IMX51CLK_PLL3SW,
+ IMX51CLK_PLL1STEP,
+ IMX51CLK_LP_APM,
+ IMX51CLK_ARM_ROOT,
+ IMX51CLK_MAIN_BUS_CLK_SRC, /* XXX */
+ IMX51CLK_MAIN_BUS_CLK,
+ IMX51CLK_EMI_SLOW_CLK_ROOT,
+ IMX51CLK_ENFC_CLK_ROOT,
+ IMX51CLK_AHB_CLK_ROOT,
+ IMX51CLK_IPG_CLK_ROOT,
+ IMX51CLK_PERCLK_ROOT,
+ IMX51CLK_DDR_CLK_ROOT,
+ IMX51CLK_ARM_AXI_CLK_ROOT,
+ IMX51CLK_ARM_AXI_A_CLK,
+ IMX51CLK_ARM_AXI_B_CLK,
+ IMX51CLK_IPU_HSP_CLK_ROOT,
+ IMX51CLK_CKIL_SYNC_CLK_ROOT,
+ IMX51CLK_USBOH3_CLK_ROOT,
+ IMX51CLK_ESDHC1_CLK_ROOT,
+ IMX51CLK_ESDHC2_CLK_ROOT,
+ IMX51CLK_ESDHC3_CLK_ROOT,
+ IMX51CLK_UART_CLK_ROOT,
+ IMX51CLK_SSI1_CLK_ROOT,
+ IMX51CLK_SSI2_CLK_ROOT,
+ IMX51CLK_SSI_EXT1_CLK_ROOT,
+ IMX51CLK_SSI_EXT2_CLK_ROOT,
+ IMX51CLK_USB_PHY_CLK_ROOT,
+ IMX51CLK_TVE_216_54_CLK_ROOT,
+ IMX51CLK_DI_CLK_ROOT,
+ IMX51CLK_SPDIF0_CLK_ROOT,
+ IMX51CLK_SPDIF1_CLK_ROOT,
+ IMX51CLK_CSPI_CLK_ROOT,
+ IMX51CLK_WRCK_CLK_ROOT,
+ IMX51CLK_LPSR_CLK_ROOT,
+ IMX51CLK_PGC_CLK_ROOT
+};
+
+u_int imx51_get_clock(enum imx51_clock);
+void imx51_clk_gating(int, int);
+int imx51_get_clk_gating(int);
+
+#endif /* _ARM_IMX_IMX51_CCMVAR_H_ */
Added: projects/efika_mx/sys/arm/freescale/imx/imx51_dpllreg.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/efika_mx/sys/arm/freescale/imx/imx51_dpllreg.h Thu Nov 8 12:45:35 2012 (r242758)
@@ -0,0 +1,104 @@
+/* $NetBSD: imx51_dpllreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Oleksandr Rybalko
+ * under sponsorship from the FreeBSD Foundation.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _IMX51_DPLLREG_H
+#define _IMX51_DPLLREG_H
+
+#include <sys/cdefs.h>
+
+/* register offset address */
+
+#define IMX51_N_DPLLS 3 /* 1..3 */
+
+#define DPLL_BASE(n) (0x83F80000 + (0x4000 * ((n)-1)))
+#define DPLL_SIZE 0x100
+
+#define DPLL_DP_CTL 0x0000 /* 0x1223 */
+#define DP_CTL_LRF 0x00000001
+#define DP_CTL_BRM 0x00000002
+#define DP_CTL_PLM 0x00000004
+#define DP_CTL_RCP 0x00000008
+#define DP_CTL_RST 0x00000010
+#define DP_CTL_UPEN 0x00000020
+#define DP_CTL_PRE 0x00000040
+#define DP_CTL_HFSM 0x00000080
+#define DP_CTL_REF_CLK_SEL_MASK 0x00000300
+#define DP_CTL_REF_CLK_SEL_COSC 0x00000200
+#define DP_CTL_REF_CLK_SEL_FPM 0x00000300
+#define DP_CTL_REF_CLK_DIV 0x00000400
+#define DP_CTL_DPDCK0_2_EN 0x00001000
+#define DP_CTL_HIGHCLK_EN DP_CTL_DPDCK0_2_EN
+#define DP_CTL_MULCTRL 0x00002000
+#define DPLL_DP_CONFIG 0x0004 /* 2 */
+#define DPLL_DP_CONFIG_APEN 0x00000002
+#define DPLL_DP_CONFIG_LDREQ 0x00000001
+#define DPLL_DP_OP 0x0008 /* 0x80 */
+#define DP_OP_PDF_SHIFT 0
+#define DP_OP_PDF_MASK (0xf << DP_OP_PDF_SHIFT)
+#define DP_OP_MFI_SHIFT 4
+#define DP_OP_MFI_MASK (0xf << DP_OP_MFI_SHIFT)
+#define DPLL_DP_MFD 0x000C /* 2 */
+#define DPLL_DP_MFN 0x0010 /* 1 */
+#define DPLL_DP_MFNMINUS 0x0014 /* 0 */
+#define DPLL_DP_MFNPLUS 0x0018 /* 0 */
+#define DPLL_DP_HFS_OP 0x001C /* 0x80 */
+#define DPLL_DP_HFS_MFD 0x0020 /* 2 */
+#define DPLL_DP_HFS_MFN 0x0024 /* 1 */
+#define DPLL_DP_TOGC 0x0028 /* 0x20000 */
+#define DPLL_DP_DESTAT 0x002C /* 1 */
+
+#endif /* _IMX51_DPLLREG_H */
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