svn commit: r229268 - projects/armv6/sys/arm/arm

[Grzegorz Bernacki]

Author: gber
Date: Mon Jan  2 09:51:12 2012
New Revision: 229268
URL: http://svn.freebsd.org/changeset/base/229268

Log:
  Little cleanup.
  
  Obtained from: Marvell, Semihalf

Modified:
  projects/armv6/sys/arm/arm/cpufunc.c
  projects/armv6/sys/arm/arm/mp_machdep.c

Modified: projects/armv6/sys/arm/arm/cpufunc.c
==============================================================================
--- projects/armv6/sys/arm/arm/cpufunc.c	Mon Jan  2 09:48:46 2012	(r229267)
+++ projects/armv6/sys/arm/arm/cpufunc.c	Mon Jan  2 09:51:12 2012	(r229268)
@@ -1352,14 +1352,12 @@ set_cpufuncs()
 		else
 			cpufuncs = pj4bv6_cpufuncs;
 
-		pj4b_config();
 		get_cachetype_cp15();
 		pmap_pte_init_mmu_v6();
 		goto out;
 	} else if (cputype == CPU_ID_ARM_88SV584X ||
 	    cputype == CPU_ID_MV88SV584X) {
 		cpufuncs = pj4bv6_cpufuncs;
-		pj4b_config();
 		get_cachetype_cp15();
 		pmap_pte_init_mmu_v6();
 		goto out;
@@ -2241,6 +2239,8 @@ pj4bv6_setup(char *args)
 {
 	int cpuctrl;
 
+	pj4b_config();
+
 	cpuctrl = CPU_CONTROL_MMU_ENABLE;
 #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
 	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
@@ -2278,6 +2278,8 @@ pj4bv7_setup(args)
 {
 	int cpuctrl;
 
+	pj4b_config();
+
 	cpuctrl = CPU_CONTROL_MMU_ENABLE;
 #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
 	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;

Modified: projects/armv6/sys/arm/arm/mp_machdep.c
==============================================================================
--- projects/armv6/sys/arm/arm/mp_machdep.c	Mon Jan  2 09:48:46 2012	(r229267)
+++ projects/armv6/sys/arm/arm/mp_machdep.c	Mon Jan  2 09:51:12 2012	(r229268)
@@ -130,9 +130,7 @@ init_secondary(int cpu)
 {
 	struct pcpu *pc;
 
-	pj4b_config();
-
-	pj4bv6_setup(NULL);
+	cpu_setup(NULL);
 
 	setttb(pmap_pa);
 	cpu_tlb_flushID();
@@ -161,15 +159,11 @@ init_secondary(int cpu)
 
 	mtx_lock_spin(&ap_boot_mtx);
 
-	cpu_dcache_wbinv_all();
-	smp_cpus++;
-	cpu_dcache_wbinv_all();
+	atomic_store_rel_int(&smp_cpus, 1);
 
 	if (smp_cpus == mp_ncpus) {
 		/* enable IPI's, tlb shootdown, freezes etc */
-		cpu_dcache_wbinv_all();
 		atomic_store_rel_int(&smp_started, 1);
-		cpu_dcache_wbinv_all();
 		smp_active = 1;
 	}