svn commit: r244707 - projects/efika_mx/sys/arm/freescale/imx
Aleksandr Rybalko
ray at FreeBSD.org
Wed Dec 26 15:41:31 UTC 2012
Author: ray
Date: Wed Dec 26 15:41:30 2012
New Revision: 244707
URL: http://svnweb.freebsd.org/changeset/base/244707
Log:
Add minimal framebuffer console driver.
Depend on graphics enabled by loader.
Sponsored by: FreeBSD Foundation
Added:
projects/efika_mx/sys/arm/freescale/imx/imx51_ipuv3.c
projects/efika_mx/sys/arm/freescale/imx/imx51_ipuv3reg.h
Added: projects/efika_mx/sys/arm/freescale/imx/imx51_ipuv3.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/efika_mx/sys/arm/freescale/imx/imx51_ipuv3.c Wed Dec 26 15:41:30 2012 (r244707)
@@ -0,0 +1,763 @@
+/*-
+ * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo at freebsd.org>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Oleksandr Rybalko
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bio.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/queue.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/time.h>
+#include <sys/timetc.h>
+#include <sys/fbio.h>
+#include <sys/consio.h>
+
+#include <sys/kdb.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/resource.h>
+#include <machine/frame.h>
+#include <machine/intr.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/fb/fbreg.h>
+#include <dev/syscons/syscons.h>
+
+#include <arm/freescale/imx/imx51_ccmvar.h>
+
+#include <arm/freescale/imx/imx51_ipuv3reg.h>
+
+#define IMX51_IPU_HSP_CLOCK 665000000
+#define IPU3FB_FONT_HEIGHT 16
+#define IPU3FB_WIDTH 1024
+#define IPU3FB_HEIGHT 600
+#define IPU3FB_BPP 2
+
+struct ipu3sc_softc {
+ device_t dev;
+ bus_addr_t pbase;
+ bus_addr_t vbase;
+
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+ bus_space_handle_t cm_ioh;
+ bus_space_handle_t dp_ioh;
+ bus_space_handle_t di0_ioh;
+ bus_space_handle_t di1_ioh;
+ bus_space_handle_t dctmpl_ioh;
+ bus_space_handle_t dc_ioh;
+ bus_space_handle_t dmfc_ioh;
+ bus_space_handle_t idmac_ioh;
+ bus_space_handle_t cpmem_ioh;
+};
+
+struct video_adapter_softc {
+ /* Videoadpater part */
+ video_adapter_t va;
+
+ intptr_t fb_addr;
+ unsigned int fb_size;
+
+ int depth;
+ unsigned int height;
+ unsigned int width;
+ unsigned int stride;
+
+ unsigned int xmargin;
+ unsigned int ymargin;
+
+ unsigned char *font;
+ int initialized;
+};
+
+static struct ipu3sc_softc *ipu3sc_softc;
+static struct video_adapter_softc va_softc;
+
+#define IPUV3_READ(ipuv3, module, reg) \
+ bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
+#define IPUV3_WRITE(ipuv3, module, reg, val) \
+ bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
+
+#define IPUV3_DEBUG 100
+
+#ifdef IPUV3_DEBUG
+#define SUBMOD_DUMP_REG(_sc, _m, _l) \
+ { \
+ int i; \
+ printf("*** " #_m " ***\n"); \
+ for (i = 0; i <= (_l); i += 4) { \
+ if ((i % 32) == 0) \
+ printf("%04x: ", i & 0xffff); \
+ printf("0x%08x%c", IPUV3_READ((_sc), _m, i), \
+ ((i + 4) % 32)?' ':'\n'); \
+ } \
+ printf("\n"); \
+ }
+#endif
+
+#ifdef IPUV3_DEBUG
+int ipuv3_debug = IPUV3_DEBUG;
+#define DPRINTFN(n,x) if (ipuv3_debug>(n)) printf x; else
+#else
+#define DPRINTFN(n,x)
+#endif
+
+static int ipu3_fb_probe(device_t);
+static int ipu3_fb_attach(device_t);
+
+static int
+ipu3_fb_malloc(struct ipu3sc_softc *sc, size_t size)
+{
+
+ sc->vbase = (uint32_t)contigmalloc(size, M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0);
+ sc->pbase = vtophys(sc->vbase);
+
+ return (0);
+}
+
+static void
+ipu3_fb_init(void *arg)
+{
+ struct ipu3sc_softc *sc = arg;
+ struct video_adapter_softc *va_sc = &va_softc;
+ int size;
+
+ size = IPU3FB_WIDTH * IPU3FB_HEIGHT * IPU3FB_BPP;
+
+ ipu3_fb_malloc(sc, size);
+
+ /* 0x000105e0 is (IPU_CPMEM_BASE + DP1 + config_ch_9 + word_2 ) */
+ bus_space_write_4(sc->iot, sc->cpmem_ioh, 0x0105e0,
+ ((sc->pbase >> 3) | ((sc->pbase >> 3) << 29)) & 0xffffffff);
+ bus_space_write_4(sc->iot, sc->cpmem_ioh, 0x0105e4,
+ ((sc->pbase >> 3) >> 3) & 0xffffffff);
+
+ va_sc->fb_addr = (intptr_t)sc->vbase;
+ va_sc->fb_size = size;
+ va_sc->stride = IPU3FB_WIDTH * IPU3FB_BPP;
+ va_sc->depth = IPU3FB_BPP * 8;
+}
+
+static int
+ipu3_fb_probe(device_t dev)
+{
+ int error;
+
+ if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
+ return (ENXIO);
+
+ device_set_desc(dev, "i.MX515 Image Processing Unit (FB)");
+
+ error = sc_probe_unit(device_get_unit(dev),
+ device_get_flags(dev) | SC_AUTODETECT_KBD);
+
+ if (error != 0)
+ return (error);
+
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+ipu3_fb_attach(device_t dev)
+{
+ struct ipu3sc_softc *sc = device_get_softc(dev);
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
+ int err;
+
+ if (ipu3sc_softc)
+ return (ENXIO);
+
+ ipu3sc_softc = sc;
+
+ device_printf(dev, "\tclock gate status is %d\n",
+ imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
+
+ sc->dev = dev;
+
+ err = (sc_attach_unit(device_get_unit(dev),
+ device_get_flags(dev) | SC_AUTODETECT_KBD));
+
+ if (err) {
+ device_printf(dev, "failed to attach syscons\n");
+ goto fail;
+ }
+
+ sc = device_get_softc(dev);
+ sc->iot = iot = fdtbus_bs_tag;
+
+ device_printf(sc->dev, ": i.MX51 IPUV3 controller\n");
+
+ /* map controller registers */
+ err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_cm;
+ sc->cm_ioh = ioh;
+
+ /* map Display Multi FIFO Controller registers */
+ err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_dmfc;
+ sc->dmfc_ioh = ioh;
+
+ /* map Display Interface 0 registers */
+ err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_di0;
+ sc->di0_ioh = ioh;
+
+ /* map Display Interface 1 registers */
+ err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_di1;
+ sc->di1_ioh = ioh;
+
+ /* map Display Processor registers */
+ err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_dp;
+ sc->dp_ioh = ioh;
+
+ /* map Display Controller registers */
+ err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_dc;
+ sc->dc_ioh = ioh;
+
+ /* map Image DMA Controller registers */
+ err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_idmac;
+ sc->idmac_ioh = ioh;
+
+ /* map CPMEM registers */
+ err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_cpmem;
+ sc->cpmem_ioh = ioh;
+
+ /* map DCTEMPL registers */
+ err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
+ if (err)
+ goto fail_retarn_dctmpl;
+ sc->dctmpl_ioh = ioh;
+
+#ifdef notyet
+ sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
+ ipuv3intr, sc);
+ if (sc->ih == NULL) {
+ device_printf(sc->dev,
+ "unable to establish interrupt at irq %d\n",
+ IMX51_INT_IPUV3);
+ return (ENXIO);
+ }
+#endif
+
+ /*
+ * We have to wait until interrupts are enabled.
+ * Mailbox relies on it to get data from VideoCore
+ */
+ ipu3_fb_init(sc);
+
+ return (0);
+
+fail:
+ return (ENXIO);
+fail_retarn_dctmpl:
+ bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
+fail_retarn_cpmem:
+ bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
+fail_retarn_idmac:
+ bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
+fail_retarn_dp:
+ bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
+fail_retarn_dc:
+ bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE);
+fail_retarn_di1:
+ bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
+fail_retarn_di0:
+ bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
+fail_retarn_dmfc:
+ bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
+fail_retarn_cm:
+ device_printf(sc->dev,
+ "failed to map registers (errno=%d)\n", err);
+ return (err);
+}
+
+static device_method_t ipu3_fb_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ipu3_fb_probe),
+ DEVMETHOD(device_attach, ipu3_fb_attach),
+
+ { 0, 0 }
+};
+
+static devclass_t ipu3_fb_devclass;
+
+static driver_t ipu3_fb_driver = {
+ "fb",
+ ipu3_fb_methods,
+ sizeof(struct ipu3sc_softc),
+};
+
+DRIVER_MODULE(ipu3fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0);
+
+/*
+ * Video driver routines and glue.
+ */
+static int ipu3fb_configure(int);
+static vi_probe_t ipu3fb_probe;
+static vi_init_t ipu3fb_init;
+static vi_get_info_t ipu3fb_get_info;
+static vi_query_mode_t ipu3fb_query_mode;
+static vi_set_mode_t ipu3fb_set_mode;
+static vi_save_font_t ipu3fb_save_font;
+static vi_load_font_t ipu3fb_load_font;
+static vi_show_font_t ipu3fb_show_font;
+static vi_save_palette_t ipu3fb_save_palette;
+static vi_load_palette_t ipu3fb_load_palette;
+static vi_set_border_t ipu3fb_set_border;
+static vi_save_state_t ipu3fb_save_state;
+static vi_load_state_t ipu3fb_load_state;
+static vi_set_win_org_t ipu3fb_set_win_org;
+static vi_read_hw_cursor_t ipu3fb_read_hw_cursor;
+static vi_set_hw_cursor_t ipu3fb_set_hw_cursor;
+static vi_set_hw_cursor_shape_t ipu3fb_set_hw_cursor_shape;
+static vi_blank_display_t ipu3fb_blank_display;
+static vi_mmap_t ipu3fb_mmap;
+static vi_ioctl_t ipu3fb_ioctl;
+static vi_clear_t ipu3fb_clear;
+static vi_fill_rect_t ipu3fb_fill_rect;
+static vi_bitblt_t ipu3fb_bitblt;
+static vi_diag_t ipu3fb_diag;
+static vi_save_cursor_palette_t ipu3fb_save_cursor_palette;
+static vi_load_cursor_palette_t ipu3fb_load_cursor_palette;
+static vi_copy_t ipu3fb_copy;
+static vi_putp_t ipu3fb_putp;
+static vi_putc_t ipu3fb_putc;
+static vi_puts_t ipu3fb_puts;
+static vi_putm_t ipu3fb_putm;
+
+static video_switch_t ipu3fbvidsw = {
+ .probe = ipu3fb_probe,
+ .init = ipu3fb_init,
+ .get_info = ipu3fb_get_info,
+ .query_mode = ipu3fb_query_mode,
+ .set_mode = ipu3fb_set_mode,
+ .save_font = ipu3fb_save_font,
+ .load_font = ipu3fb_load_font,
+ .show_font = ipu3fb_show_font,
+ .save_palette = ipu3fb_save_palette,
+ .load_palette = ipu3fb_load_palette,
+ .set_border = ipu3fb_set_border,
+ .save_state = ipu3fb_save_state,
+ .load_state = ipu3fb_load_state,
+ .set_win_org = ipu3fb_set_win_org,
+ .read_hw_cursor = ipu3fb_read_hw_cursor,
+ .set_hw_cursor = ipu3fb_set_hw_cursor,
+ .set_hw_cursor_shape = ipu3fb_set_hw_cursor_shape,
+ .blank_display = ipu3fb_blank_display,
+ .mmap = ipu3fb_mmap,
+ .ioctl = ipu3fb_ioctl,
+ .clear = ipu3fb_clear,
+ .fill_rect = ipu3fb_fill_rect,
+ .bitblt = ipu3fb_bitblt,
+ .diag = ipu3fb_diag,
+ .save_cursor_palette = ipu3fb_save_cursor_palette,
+ .load_cursor_palette = ipu3fb_load_cursor_palette,
+ .copy = ipu3fb_copy,
+ .putp = ipu3fb_putp,
+ .putc = ipu3fb_putc,
+ .puts = ipu3fb_puts,
+ .putm = ipu3fb_putm,
+};
+
+VIDEO_DRIVER(ipu3fb, ipu3fbvidsw, ipu3fb_configure);
+
+extern sc_rndr_sw_t txtrndrsw;
+RENDERER(ipu3fb, 0, txtrndrsw, gfb_set);
+RENDERER_MODULE(ipu3fb, gfb_set);
+
+static uint16_t ipu3fb_static_window[ROW*COL];
+extern u_char dflt_font_16[];
+
+static int
+ipu3fb_configure(int flags)
+{
+ struct video_adapter_softc *sc;
+
+ sc = &va_softc;
+
+ if (sc->initialized)
+ return 0;
+
+ sc->height = IPU3FB_HEIGHT;
+ sc->width = IPU3FB_WIDTH;
+
+ ipu3fb_init(0, &sc->va, 0);
+
+ sc->initialized = 1;
+
+ return (0);
+}
+
+static int
+ipu3fb_probe(int unit, video_adapter_t **adp, void *arg, int flags)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_init(int unit, video_adapter_t *adp, int flags)
+{
+ struct video_adapter_softc *sc;
+ video_info_t *vi;
+
+ sc = (struct video_adapter_softc *)adp;
+ vi = &adp->va_info;
+
+ vid_init_struct(adp, "ipu3fb", -1, unit);
+
+ sc->font = dflt_font_16;
+ vi->vi_cheight = IPU3FB_FONT_HEIGHT;
+ vi->vi_cwidth = 8;
+ vi->vi_width = sc->width/8;
+ vi->vi_height = sc->height/vi->vi_cheight;
+
+ /*
+ * Clamp width/height to syscons maximums
+ */
+ if (vi->vi_width > COL)
+ vi->vi_width = COL;
+ if (vi->vi_height > ROW)
+ vi->vi_height = ROW;
+
+ sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2;
+ sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight))/2;
+
+ adp->va_window = (vm_offset_t) ipu3fb_static_window;
+ adp->va_flags |= V_ADP_FONT /* | V_ADP_COLOR | V_ADP_MODECHANGE */;
+
+ vid_register(&sc->va);
+
+ return (0);
+}
+
+static int
+ipu3fb_get_info(video_adapter_t *adp, int mode, video_info_t *info)
+{
+ bcopy(&adp->va_info, info, sizeof(*info));
+ return (0);
+}
+
+static int
+ipu3fb_query_mode(video_adapter_t *adp, video_info_t *info)
+{
+ return (0);
+}
+
+static int
+ipu3fb_set_mode(video_adapter_t *adp, int mode)
+{
+ return (0);
+}
+
+static int
+ipu3fb_save_font(video_adapter_t *adp, int page, int size, int width,
+ u_char *data, int c, int count)
+{
+ return (0);
+}
+
+static int
+ipu3fb_load_font(video_adapter_t *adp, int page, int size, int width,
+ u_char *data, int c, int count)
+{
+ struct video_adapter_softc *sc = (struct video_adapter_softc *)adp;
+
+ sc->font = data;
+
+ return (0);
+}
+
+static int
+ipu3fb_show_font(video_adapter_t *adp, int page)
+{
+ return (0);
+}
+
+static int
+ipu3fb_save_palette(video_adapter_t *adp, u_char *palette)
+{
+ return (0);
+}
+
+static int
+ipu3fb_load_palette(video_adapter_t *adp, u_char *palette)
+{
+ return (0);
+}
+
+static int
+ipu3fb_set_border(video_adapter_t *adp, int border)
+{
+ return (ipu3fb_blank_display(adp, border));
+}
+
+static int
+ipu3fb_save_state(video_adapter_t *adp, void *p, size_t size)
+{
+ return (0);
+}
+
+static int
+ipu3fb_load_state(video_adapter_t *adp, void *p)
+{
+ return (0);
+}
+
+static int
+ipu3fb_set_win_org(video_adapter_t *adp, off_t offset)
+{
+ return (0);
+}
+
+static int
+ipu3fb_read_hw_cursor(video_adapter_t *adp, int *col, int *row)
+{
+ *col = *row = 0;
+
+ return (0);
+}
+
+static int
+ipu3fb_set_hw_cursor(video_adapter_t *adp, int col, int row)
+{
+ return (0);
+}
+
+static int
+ipu3fb_set_hw_cursor_shape(video_adapter_t *adp, int base, int height,
+ int celsize, int blink)
+{
+ return (0);
+}
+
+static int
+ipu3fb_blank_display(video_adapter_t *adp, int mode)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr,
+ int prot, vm_memattr_t *memattr)
+{
+ struct video_adapter_softc *sc;
+
+ sc = (struct video_adapter_softc *)adp;
+
+ /*
+ * This might be a legacy VGA mem request: if so, just point it at the
+ * framebuffer, since it shouldn't be touched
+ */
+ if (offset < sc->stride * sc->height) {
+ *paddr = sc->fb_addr + offset;
+ return (0);
+ }
+
+ return (EINVAL);
+}
+
+static int
+ipu3fb_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_clear(video_adapter_t *adp)
+{
+
+ return (ipu3fb_blank_display(adp, 0));
+}
+
+static int
+ipu3fb_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_bitblt(video_adapter_t *adp, ...)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_diag(video_adapter_t *adp, int level)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_save_cursor_palette(video_adapter_t *adp, u_char *palette)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_load_cursor_palette(video_adapter_t *adp, u_char *palette)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a,
+ int size, int bpp, int bit_ltor, int byte_ltor)
+{
+
+ return (0);
+}
+
+static int
+ipu3fb_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a)
+{
+ struct video_adapter_softc *sc;
+ int col, row;
+ int i, j, k;
+ uint8_t *addr;
+ u_char *p;
+ uint16_t fg, bg, color;
+
+ sc = (struct video_adapter_softc *)adp;
+
+ if (sc->fb_addr == 0)
+ return (0);
+ row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight;
+ col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth;
+ p = sc->font + c * IPU3FB_FONT_HEIGHT;
+ addr = (uint8_t *)sc->fb_addr
+ + (row + sc->ymargin) * (sc->stride)
+ + IPU3FB_BPP * (col + sc->xmargin);
+
+ /*
+ * FIXME: hardcoded
+ */
+ bg = 0x0000;
+ fg = 0xffff;
+
+ for (i = 0; i < IPU3FB_FONT_HEIGHT; i++) {
+ for (j = 0, k = 7; j < 8; j++, k--) {
+ if ((p[i] & (1 << k)) == 0)
+ color = bg;
+ else
+ color = fg;
+
+ addr[IPU3FB_BPP * j] = color;
+ addr[IPU3FB_BPP * j + 1] = color;
+ addr[IPU3FB_BPP * j + 2] = color;
+ }
+
+ addr += (sc->stride);
+ }
+
+ return (0);
+}
+
+static int
+ipu3fb_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ ipu3fb_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8);
+
+ return (0);
+}
+
+static int
+ipu3fb_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image,
+ uint32_t pixel_mask, int size, int width)
+{
+
+ return (0);
+}
+
+/*
+ * Define a stub keyboard driver in case one hasn't been
+ * compiled into the kernel
+ */
+#include <sys/kbio.h>
+#include <dev/kbd/kbdreg.h>
+
+static int dummy_kbd_configure(int flags);
+
+keyboard_switch_t ipu3dummysw;
+
+static int
+dummy_kbd_configure(int flags)
+{
+
+ return (0);
+}
+KEYBOARD_DRIVER(ipu3dummy, ipu3dummysw, dummy_kbd_configure);
Added: projects/efika_mx/sys/arm/freescale/imx/imx51_ipuv3reg.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/efika_mx/sys/arm/freescale/imx/imx51_ipuv3reg.h Wed Dec 26 15:41:30 2012 (r244707)
@@ -0,0 +1,919 @@
+/* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */
+/*
+ * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Oleksandr Rybalko
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _ARM_IMX_IMX51_IPUV3REG_H
+#define _ARM_IMX_IMX51_IPUV3REG_H
+
+/* register offset address */
+
+/*
+ * CM
+ * Control Module
+ */
+#define IPU_CM_CONF 0x00000000
+#define CM_CONF_CSI_SEL 0x80000000
+#define CM_CONF_IC_INPUT 0x40000000
+#define CM_CONF_CSI1_DATA_SOURCE 0x20000000
+#define CM_CONF_CSI0_DATA_SOURCE 0x10000000
+#define CM_CONF_VDI_DMFC_SYNC 0x08000000
+#define CM_CONF_IC_DMFC_SYNC 0x04000000
+#define CM_CONF_IC_DMFC_SEL 0x02000000
+#define CM_CONF_ISP_DOUBLE_FLOW 0x01000000
+#define CM_CONF_IDMAC_DISABLE 0x00400000
+#define CM_CONF_IPU_DIAGBUS_ON 0x00200000
+#define CM_CONF_IPU_DIAGBUS_MODE 0x001f0000
+#define CM_CONF_VDI_EN 0x00001000
+#define CM_CONF_SISG_EN 0x00000800
+#define CM_CONF_DMFC_EN 0x00000400
+#define CM_CONF_DC_EN 0x00000200
+#define CM_CONF_SMFC_EN 0x00000100
+#define CM_CONF_DI1_EN 0x00000080
+#define CM_CONF_DI0_EN 0x00000040
+#define CM_CONF_DP_EN 0x00000020
+#define CM_CONF_ISP_EN 0x00000010
+#define CM_CONF_IRT_EN 0x00000008
+#define CM_CONF_IC_EN 0x00000004
+#define CM_CONF_CSI1_EN 0x00000002
+#define CM_CONF_CSI0_EN 0x00000001
+#define IPU_SISG_CTRL0 0x00000004
+#define IPU_SISG_CTRL1 0x00000008
+#define IPU_CM_INT_CTRL_1 0x0000003c
+#define IPU_CM_INT_CTRL_2 0x00000040
+#define IPU_CM_INT_CTRL_3 0x00000044
+#define IPU_CM_INT_CTRL_4 0x00000048
+#define IPU_CM_INT_CTRL_5 0x0000004c
+#define IPU_CM_INT_CTRL_6 0x00000050
+#define IPU_CM_INT_CTRL_7 0x00000054
+#define IPU_CM_INT_CTRL_8 0x00000058
+#define IPU_CM_INT_CTRL_9 0x0000005c
+#define IPU_CM_INT_CTRL_10 0x00000060
+#define IPU_CM_INT_CTRL_11 0x00000064
+#define IPU_CM_INT_CTRL_12 0x00000068
+#define IPU_CM_INT_CTRL_13 0x0000006c
+#define IPU_CM_INT_CTRL_14 0x00000070
+#define IPU_CM_INT_CTRL_15 0x00000074
+#define IPU_CM_SDMA_EVENT_1 0x00000078
+#define IPU_CM_SDMA_EVENT_2 0x0000007c
+#define IPU_CM_SDMA_EVENT_3 0x00000080
+#define IPU_CM_SDMA_EVENT_4 0x00000084
+#define IPU_CM_SDMA_EVENT_7 0x00000088
+#define IPU_CM_SDMA_EVENT_8 0x0000008c
+#define IPU_CM_SDMA_EVENT_11 0x00000090
+#define IPU_CM_SDMA_EVENT_12 0x00000094
+#define IPU_CM_SDMA_EVENT_13 0x00000098
+#define IPU_CM_SDMA_EVENT_14 0x0000009c
+#define IPU_CM_SRM_PRI1 0x000000a0
+#define IPU_CM_SRM_PRI2 0x000000a4
+#define IPU_CM_FS_PROC_FLOW1 0x000000a8
+#define IPU_CM_FS_PROC_FLOW2 0x000000ac
+#define IPU_CM_FS_PROC_FLOW3 0x000000b0
+#define IPU_CM_FS_DISP_FLOW1 0x000000b4
+#define IPU_CM_FS_DISP_FLOW2 0x000000b8
+#define IPU_CM_SKIP 0x000000bc
+#define IPU_CM_DISP_ALT_CONF 0x000000c0
+#define IPU_CM_DISP_GEN 0x000000c4
+#define CM_DISP_GEN_DI0_COUNTER_RELEASE 0x01000000
+#define CM_DISP_GEN_DI1_COUNTER_RELEASE 0x00800000
+#define CM_DISP_GEN_MCU_MAX_BURST_STOP 0x00400000
+#define CM_DISP_GEN_MCU_T_SHIFT 18
+#define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT)
+#define IPU_CM_DISP_ALT1 0x000000c8
+#define IPU_CM_DISP_ALT2 0x000000cc
+#define IPU_CM_DISP_ALT3 0x000000d0
+#define IPU_CM_DISP_ALT4 0x000000d4
+#define IPU_CM_SNOOP 0x000000d8
+#define IPU_CM_MEM_RST 0x000000dc
+#define CM_MEM_START 0x80000000
+#define CM_MEM_EN 0x007fffff
+#define IPU_CM_PM 0x000000e0
+#define IPU_CM_GPR 0x000000e4
+#define CM_GPR_IPU_CH_BUF1_RDY1_CLR 0x80000000
+#define CM_GPR_IPU_CH_BUF1_RDY0_CLR 0x40000000
+#define CM_GPR_IPU_CH_BUF0_RDY1_CLR 0x20000000
+#define CM_GPR_IPU_CH_BUF0_RDY0_CLR 0x10000000
+#define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR 0x08000000
+#define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR 0x04000000
+#define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR 0x02000000
+#define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR 0x01000000
+#define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS 0x00800000
+#define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS 0x00400000
+#define CM_GPR_IPU_CH_BUF2_RDY1_CLR 0x00200000
+#define CM_GPR_IPU_CH_BUF2_RDY0_CLR 0x00100000
+#define CM_GPR_IPU_GP(n) __BIT((n))
+#define IPU_CM_CH_DB_MODE_SEL_0 0x00000150
+#define IPU_CM_CH_DB_MODE_SEL_1 0x00000154
+#define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168
+#define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c
+#define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178
+#define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c
+#define IPU_CM_INT_STAT_1 0x00000200
+#define IPU_CM_INT_STAT_2 0x00000204
+#define IPU_CM_INT_STAT_3 0x00000208
+#define IPU_CM_INT_STAT_4 0x0000020c
+#define IPU_CM_INT_STAT_5 0x00000210
+#define IPU_CM_INT_STAT_6 0x00000214
+#define IPU_CM_INT_STAT_7 0x00000218
+#define IPU_CM_INT_STAT_8 0x0000021c
+#define IPU_CM_INT_STAT_9 0x00000220
+#define IPU_CM_INT_STAT_10 0x00000224
+#define IPU_CM_INT_STAT_11 0x00000228
+#define IPU_CM_INT_STAT_12 0x0000022c
+#define IPU_CM_INT_STAT_13 0x00000230
+#define IPU_CM_INT_STAT_14 0x00000234
+#define IPU_CM_INT_STAT_15 0x00000238
+#define IPU_CM_CUR_BUF_0 0x0000023c
+#define IPU_CM_CUR_BUF_1 0x00000240
+#define IPU_CM_ALT_CUR_BUF_0 0x00000244
+#define IPU_CM_ALT_CUR_BUF_1 0x00000248
+#define IPU_CM_SRM_STAT 0x0000024c
+#define IPU_CM_PROC_TASKS_STAT 0x00000250
+#define IPU_CM_DISP_TASKS_STAT 0x00000254
+#define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258
+#define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c
+#define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260
+#define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264
+#define IPU_CM_CH_BUF0_RDY0 0x00000268
+#define IPU_CM_CH_BUF0_RDY1 0x0000026c
+#define IPU_CM_CH_BUF1_RDY0 0x00000270
+#define IPU_CM_CH_BUF1_RDY1 0x00000274
+#define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278
+#define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c
+#define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280
+#define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284
+#define IPU_CM_CH_BUF2_RDY0 0x00000288
+#define IPU_CM_CH_BUF2_RDY1 0x0000028c
+
+/*
+ * IDMAC
+ * Image DMA Controller
+ */
+#define IPU_IDMAC_CONF 0x00000000
+#define IPU_IDMAC_CH_EN_1 0x00000004
+#define IPU_IDMAC_CH_EN_2 0x00000008
+#define IPU_IDMAC_SEP_ALPHA 0x0000000c
+#define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010
+#define IPU_IDMAC_CH_PRI_1 0x00000014
+#define IPU_IDMAC_CH_PRI_2 0x00000018
+#define IPU_IDMAC_WM_EN_1 0x0000001c
+#define IPU_IDMAC_WM_EN_2 0x00000020
+#define IPU_IDMAC_LOCK_EN_1 0x00000024
+#define IPU_IDMAC_LOCK_EN_2 0x00000028
+#define IPU_IDMAC_SUB_ADDR_0 0x0000002c
+#define IPU_IDMAC_SUB_ADDR_1 0x00000030
+#define IPU_IDMAC_SUB_ADDR_2 0x00000034
+#define IPU_IDMAC_SUB_ADDR_3 0x00000038
+#define IPU_IDMAC_SUB_ADDR_4 0x0000003c
+#define IPU_IDMAC_BNDM_EN_1 0x00000040
+#define IPU_IDMAC_BNDM_EN_2 0x00000044
+#define IPU_IDMAC_SC_CORD 0x00000048
+#define IPU_IDMAC_SC_CORD1 0x0000004c
+#define IPU_IDMAC_CH_BUSY_1 0x00000100
+#define IPU_IDMAC_CH_BUSY_2 0x00000104
+
+#define CH_PANNEL_BG 23
+#define CH_PANNEL_FG 27
+
+/*
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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