svn commit: r227772 - in projects/pseries: amd64/amd64 amd64/conf amd64/ia32 amd64/include amd64/linux32 arm/arm arm/at91 arm/conf arm/econa arm/include arm/mv arm/sa11x0 arm/xscale/i80321 arm/xsca...

[Peter Grehan]

Hi Nathan,

  (cc'ing Bryan, virtio author)

>> One thing to look out for is that the virtio spec has PCI register
>> access in host-order, so you may need to switch in big-endian bus ops.
...
> Is it worth making some generic way to avoid regular bus accessors? It
> also needs to avoid regular bus dma calls, since the spec indicates
> finger-of-God accesses that bypass any emulated IOMMU that busdma would
> ordinarily try to use.

  The PCI interface for virtio specifies i/o space for device register 
access - that still needs bus space on x86 to get the right instructions 
issued. But, there's also a recent proposal to have additional BARs 
accessed via MMIO and not i/o. At least on x86 this still fits in fine 
with the standard PCI driver model.

  Is the p-series i/f a memory-mapped local-bus style of access, or is 
it via a pseudo PCI bus ?

later,

Peter.