svn commit: r221614 - projects/largeSMP/sys/powerpc/include

[Kostik Belousov]

On Fri, May 13, 2011 at 05:45:52PM +0200, Attilio Rao wrote:
> 2011/5/13 Kostik Belousov <kostikbel at gmail.com>:
> > On Fri, May 13, 2011 at 03:50:47PM +0200, Attilio Rao wrote:
> >> The per-cpu stuff also, is read only. The pm_active objects are
> >> protected by VM locks.
> >
> > pm_active is not protected by any vm lock. It is set and cleared
> > unlocked in the context switch code. But, the ctx switch only needs
> > to set and clear a single bit at the time of switch, that makes
> > the atomic operations sufficient for consistency.
> >
> > I had a WIP on the Intel PCID, were such protection was not enough,
> > unfortunately.
> 
> You are indeed right, sorry.
> 
> What trouble were you having in your case, just for the sake of my
> curiosity, if you can share?

PCID is a feature where the cpu tag each TLB entry with some process ID
(not Unix PID). When doing context switch, reload of %cr3 does not
invalidate the TLB on the core, but instead rewrite the "current ID"
value to use for tag fetch and store.

For each pmap, when page entry is modified, we need to clear the TLB entry
on all cores (threads) that could have the mapping in TLB. So each pmap
grows additional cpu set which indicates such cores.

In the microbenchmark, use of PCID gives two times speed increase
of context switch.

I do not remember exact details right now, but I did need a NAND
operation on cpu sets with both operands potentially having more
then one bit active.

Currently the work is stalled, I lost access to the Westmere machine
for testing.
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