svn commit: r223767 - in projects/llvm-ia64: contrib/llvm/lib/Target/IA64 lib/clang/include

[Marcel Moolenaar]

On Jul 4, 2011, at 1:10 PM, Roman Divacky wrote:

> First of all.. big wow :) This is awesome progress.

Thanks!

>> +void
>> +IA64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
>> +    MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg,
>> +    unsigned SrcReg, bool KillSrc) const
>> +{
>> +  bool GRDest = IA64::GRRegClass.contains(DestReg);
>> +  bool GRSrc  = IA64::GRRegClass.contains(SrcReg);
>> +
>> +  if (GRDest && GRSrc) {
>> +    MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(IA64::ADD), DestReg);
>> +    MIB.addReg(IA64::R0);
>> +    MIB.addReg(SrcReg, getKillRegState(KillSrc));
>> +    return;
>> +  }
>> +
>> +  llvm_unreachable(__func__);
>> +}
> 
> copyPhysReg() done via ADD ? Is this just some temporary measure to achieve
> emission of any code? I am not even sure how this can work. The IR should
> require you to lower the ISD::ADD node, right? You don't seem to be doing that.

On ia64 there's no copy instruction in H/W. The assembler defines
"mov r1=r2" as a pseudo-op of "adds r1=0,r2". Since I didn't want
to introduce an immediate operand yet, I simply used r0, which is
hardwired as 0. The result is the same...

As for the lowering: the add is eliminated shortly after it's
created by virtue of copy elimination, CSE and/or GVN on the
selection DAG. We know we can lower ADDs anyway, because it's
in the assembly output :-)

-- 
Marcel Moolenaar
marcel at xcllnt.net