svn commit: r225146 - in projects/armv6/sys: arm/arm arm/include
conf
Grzegorz Bernacki
gber at FreeBSD.org
Wed Aug 24 14:12:36 UTC 2011
Author: gber
Date: Wed Aug 24 14:12:35 2011
New Revision: 225146
URL: http://svn.freebsd.org/changeset/base/225146
Log:
Added initial Cortex-Axx support.
Submitted by: Damjan Marion
Modified:
projects/armv6/sys/arm/arm/identcpu.c
projects/armv6/sys/arm/arm/locore.S
projects/armv6/sys/arm/arm/swtch.S
projects/armv6/sys/arm/include/armreg.h
projects/armv6/sys/arm/include/cpuconf.h
projects/armv6/sys/arm/include/md_var.h
projects/armv6/sys/arm/include/pmap.h
projects/armv6/sys/conf/files.arm
projects/armv6/sys/conf/options.arm
Modified: projects/armv6/sys/arm/arm/identcpu.c
==============================================================================
--- projects/armv6/sys/arm/arm/identcpu.c Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/arm/identcpu.c Wed Aug 24 14:12:35 2011 (r225146)
@@ -235,6 +235,17 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S",
generic_steppings },
+ { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEXA, "Cortex A8-r1",
+ generic_steppings },
+ { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEXA, "Cortex A8-r2",
+ generic_steppings },
+ { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEXA, "Cortex A8-r3",
+ generic_steppings },
+ { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEXA, "Cortex A9-r1",
+ generic_steppings },
+ { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEXA, "Cortex A9-r2",
+ generic_steppings },
+
{ CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
sa110_steppings },
{ CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
@@ -336,6 +347,7 @@ const struct cpu_classtab cpu_classes[]
{ "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
{ "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
{ "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */
+ { "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */
{ "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */
{ "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
{ "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
Modified: projects/armv6/sys/arm/arm/locore.S
==============================================================================
--- projects/armv6/sys/arm/arm/locore.S Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/arm/locore.S Wed Aug 24 14:12:35 2011 (r225146)
@@ -162,7 +162,7 @@ Lunmapped:
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
-#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B)
+#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -172,7 +172,7 @@ Lunmapped:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
-#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B)
+#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
Modified: projects/armv6/sys/arm/arm/swtch.S
==============================================================================
--- projects/armv6/sys/arm/arm/swtch.S Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/arm/swtch.S Wed Aug 24 14:12:35 2011 (r225146)
@@ -141,7 +141,7 @@ ENTRY(cpu_throw)
/* Switch to lwp0 context */
ldr r9, .Lcpufuncs
-#if !defined(CPU_ARM11) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
mov lr, pc
ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
#endif
@@ -335,7 +335,7 @@ ENTRY(cpu_switch)
cmpeq r0, r5 /* Same DACR? */
beq .Lcs_context_switched /* yes! */
-#if !defined(CPU_ARM11) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
/*
* Definately need to flush the cache.
*/
@@ -367,7 +367,7 @@ ENTRY(cpu_switch)
beq .Lcs_same_vector
str r0, [r7] /* Otherwise, update it */
-#if !defined(CPU_ARM11) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
/*
* Need to sync the cache to make sure that last store is
* visible to the MMU.
Modified: projects/armv6/sys/arm/include/armreg.h
==============================================================================
--- projects/armv6/sys/arm/include/armreg.h Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/include/armreg.h Wed Aug 24 14:12:35 2011 (r225146)
@@ -146,6 +146,11 @@
#define CPU_ID_ARM1026EJS 0x4106a260
#define CPU_ID_ARM1136JS 0x4107b360
#define CPU_ID_ARM1136JSR1 0x4117b360
+#define CPU_ID_CORTEXA8R1 0x411fc080
+#define CPU_ID_CORTEXA8R2 0x412fc080
+#define CPU_ID_CORTEXA8R3 0x413fc080
+#define CPU_ID_CORTEXA9R1 0x411fc090
+#define CPU_ID_CORTEXA9R2 0x412fc090
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
Modified: projects/armv6/sys/arm/include/cpuconf.h
==============================================================================
--- projects/armv6/sys/arm/include/cpuconf.h Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/include/cpuconf.h Wed Aug 24 14:12:35 2011 (r225146)
@@ -64,6 +64,7 @@
defined(CPU_FA526) + \
defined(CPU_FA626TE) + \
defined(CPU_XSCALE_IXP425)) + \
+ defined(CPU_CORTEXA) + \
defined(CPU_MV_PJ4B)
/*
@@ -93,12 +94,18 @@
#define ARM_ARCH_6 0
#endif
-#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6)
+#if defined(CPU_CORTEXA)
+#define ARM_ARCH_7A 1
+#else
+#define ARM_ARCH_7A 0
+#endif
+
+#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A)
#if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
#error ARM_NARCH is 0
#endif
-#if ARM_ARCH_5 || ARM_ARCH_6
+#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A
/*
* We could support Thumb code on v4T, but the lack of clean interworking
* makes that hard.
@@ -116,6 +123,8 @@
*
* ARM_MMU_V6 ARMv6 MMU.
*
+ * ARM_MMU_V7 ARMv7 MMU.
+ *
* ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
* ARM MMU, but has no write-through cache mode.
*
@@ -144,6 +153,12 @@
#define ARM_MMU_V6 0
#endif
+#if defined(CPU_CORTEXA)
+#define ARM_MMU_V7 1
+#else
+#define ARM_MMU_V7 0
+#endif
+
#if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
defined(CPU_IXP12X0))
#define ARM_MMU_SA1 1
@@ -160,7 +175,7 @@
#endif
#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_V6 + \
- ARM_MMU_SA1 + ARM_MMU_XSCALE)
+ ARM_MMU_V7 + ARM_MMU_SA1 + ARM_MMU_XSCALE)
#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
#error ARM_NMMUS is 0
#endif
Modified: projects/armv6/sys/arm/include/md_var.h
==============================================================================
--- projects/armv6/sys/arm/include/md_var.h Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/include/md_var.h Wed Aug 24 14:12:35 2011 (r225146)
@@ -62,6 +62,7 @@ enum cpu_class {
CPU_CLASS_ARM9EJS,
CPU_CLASS_ARM10E,
CPU_CLASS_ARM10EJ,
+ CPU_CLASS_CORTEXA,
CPU_CLASS_SA1,
CPU_CLASS_XSCALE,
CPU_CLASS_ARM11J,
Modified: projects/armv6/sys/arm/include/pmap.h
==============================================================================
--- projects/armv6/sys/arm/include/pmap.h Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/arm/include/pmap.h Wed Aug 24 14:12:35 2011 (r225146)
@@ -297,7 +297,7 @@ extern int pmap_needs_pte_sync;
/*
* User-visible names for the ones that vary with MMU class.
*/
-#if ARM_MMU_V6 == 1
+#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
#define L2_AP(x) (L2_AP0(x))
#else
#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
@@ -343,7 +343,7 @@ extern int pmap_needs_pte_sync;
#define L1_C_PROTO L1_C_PROTO_xscale
#define L2_S_PROTO L2_S_PROTO_xscale
-#elif ARM_MMU_V6 == 1
+#elif (ARM_MMU_V6 + ARM_MMU_V7) != 0
#define L2_S_PROT_U (L2_AP0(2)) /* user access */
#define L2_S_PROT_R (L2_APX|L2_AP0(1)) /* read access */
@@ -399,7 +399,8 @@ extern int pmap_needs_pte_sync;
* These macros return various bits based on kernel/user and protection.
* Note that the compiler will usually fold these at compile time.
*/
-#if ARM_MMU_V6 == 0
+#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
+
#define L1_S_PROT_U (L1_S_AP(AP_U))
#define L1_S_PROT_W (L1_S_AP(AP_W))
#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
@@ -495,7 +496,7 @@ extern pt_entry_t pte_l2_s_proto;
extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
-#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
+#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
void pmap_zero_page_generic(vm_paddr_t, int, int);
@@ -509,7 +510,7 @@ void pmap_pte_init_arm9(void);
#if defined(CPU_ARM10)
void pmap_pte_init_arm10(void);
#endif /* CPU_ARM10 */
-#if defined(ARM_MMU_V6)
+#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
void pmap_pte_init_mmu_v6(void);
#endif /* CPU_ARM11 */
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
Modified: projects/armv6/sys/conf/files.arm
==============================================================================
--- projects/armv6/sys/conf/files.arm Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/conf/files.arm Wed Aug 24 14:12:35 2011 (r225146)
@@ -8,7 +8,7 @@ arm/arm/blockio.S standard
arm/arm/bootconfig.c standard
arm/arm/bus_space_asm_generic.S standard
arm/arm/busdma_machdep.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0
-arm/arm/busdma_machdep-v6.c optional cpu_arm11 | cpu_mv_pj4b
+arm/arm/busdma_machdep-v6.c optional cpu_arm11 | cpu_cortexa | cpu_mv_pj4b
arm/arm/copystr.S standard
arm/arm/cpufunc.c standard
arm/arm/cpufunc_asm.S standard
@@ -35,7 +35,7 @@ arm/arm/minidump_machdep.c optional mem
arm/arm/mp_machdep.c optional smp
arm/arm/nexus.c standard
arm/arm/pmap.c optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 | cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0
-arm/arm/pmap-v6.c optional cpu_arm11 | cpu_mv_pj4b
+arm/arm/pmap-v6.c optional cpu_arm11 | cpu_cortexa | cpu_mv_pj4b
arm/arm/setcpsr.S standard
arm/arm/setstack.s standard
arm/arm/stack_machdep.c optional ddb | stack
Modified: projects/armv6/sys/conf/options.arm
==============================================================================
--- projects/armv6/sys/conf/options.arm Wed Aug 24 14:11:00 2011 (r225145)
+++ projects/armv6/sys/conf/options.arm Wed Aug 24 14:12:35 2011 (r225146)
@@ -10,6 +10,7 @@ COUNTS_PER_SEC opt_timer.h
CPU_ARM9 opt_global.h
CPU_ARM9E opt_global.h
CPU_ARM11 opt_global.h
+CPU_CORTEXA opt_global.h
CPU_FA526 opt_global.h
CPU_FA626TE opt_global.h
CPU_MV_PJ4B opt_global.h
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