svn commit: r358408 - head/contrib/llvm-project/llvm/lib/Target/RISCV

[Brooks Davis]

Author: brooks
Date: Thu Feb 27 20:08:46 2020
New Revision: 358408
URL: https://svnweb.freebsd.org/changeset/base/358408

Log:
  Merge commit 7214f7a79 from llvm git (by Sam Elliott):
  
    [RISCV] Lower llvm.trap and llvm.debugtrap
  
    Summary:
    Until this commit, these have lowered to a call to abort().
  
    `llvm.trap()` now lowers to `unimp`, which should trap on all systems.
  
    `llvm.debugtrap()` now lowers to `ebreak`, which is exactly what this
    instruction is for.
  
    Reviewers: asb, luismarques
  
    Reviewed By: asb
  
    Tags: #llvm
  
    Differential Revision: https://reviews.llvm.org/D69390
  
  This fixes miscompilation resulting in linking failures with
  INVARIANTS disabled.
  
  Reviewed by:	dim
  Differential Revision:	https://reviews.freebsd.org/D23857

Modified:
  head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td

Modified: head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
==============================================================================
--- head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp	Thu Feb 27 19:59:17 2020	(r358407)
+++ head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp	Thu Feb 27 20:08:46 2020	(r358408)
@@ -185,6 +185,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetM
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
                      Subtarget.is64Bit() ? Legal : Custom);
 
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
+
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);

Modified: head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td
==============================================================================
--- head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td	Thu Feb 27 19:59:17 2020	(r358407)
+++ head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td	Thu Feb 27 20:08:46 2020	(r358408)
@@ -1075,6 +1075,16 @@ let Predicates = [IsRV32], usesCustomInserter = 1, has
 mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in
 def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">;
 
+/// traps
+
+// We lower `trap` to `unimp`, as this causes a hard exception on nearly all
+// systems.
+def : Pat<(trap), (UNIMP)>;
+
+// We lower `debugtrap` to `ebreak`, as this will get the attention of the
+// debugger if possible.
+def : Pat<(debugtrap), (EBREAK)>;
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//