svn commit: r358174 - head/sys/dev/pci

[Konstantin Belousov]

Author: kib
Date: Thu Feb 20 17:08:52 2020
New Revision: 358174
URL: https://svnweb.freebsd.org/changeset/base/358174

Log:
  Add more values for PCI capabilities, PCIe extended capabilities, and subclasses.
  
  Taken from
  https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
  
  Submitted by:	Dmitry Luhtionov <dmitryluhtionov at gmail.com>
  MFC after:	1 week

Modified:
  head/sys/dev/pci/pcireg.h

Modified: head/sys/dev/pci/pcireg.h
==============================================================================
--- head/sys/dev/pci/pcireg.h	Thu Feb 20 16:58:57 2020	(r358173)
+++ head/sys/dev/pci/pcireg.h	Thu Feb 20 17:08:52 2020	(r358174)
@@ -151,6 +151,7 @@
 #define	PCIY_SATA	0x12	/* SATA */
 #define	PCIY_PCIAF	0x13	/* PCI Advanced Features */
 #define	PCIY_EA		0x14	/* PCI Extended Allocation */
+#define	PCIY_FPB	0x15	/* Flattening Portal Bridge */
 
 /* Extended Capability Register Fields */
 
@@ -194,6 +195,20 @@
 #define	PCIZ_LN_REQ	0x001c	/* LN Requester */
 #define	PCIZ_DPC	0x001d	/* Downstream Port Containment */
 #define	PCIZ_L1PM	0x001e	/* L1 PM Substates */
+#define	PCIZ_PTM	0x001f	/* Precision Time Measurement */
+#define	PCIZ_M_PCIE	0x0020	/* PCIe over M-PHY */
+#define	PCIZ_FRS	0x0021	/* FRS Queuing */
+#define	PCIZ_RTR	0x0022	/* Readiness Time Reporting */
+#define	PCIZ_DVSEC	0x0023	/* Designated Vendor-Specific */
+#define	PCIZ_VF_REBAR	0x0024	/* VF Resizable BAR */
+#define	PCIZ_DLNK	0x0025	/* Data Link Feature */
+#define	PCIZ_16GT	0x0026	/* Physical Layer 16.0 GT/s */
+#define	PCIZ_LMR	0x0027	/* Lane Margining at Receiver */
+#define	PCIZ_HIER_ID	0x0028	/* Hierarchy ID */
+#define	PCIZ_NPEM	0x0029	/* Native PCIe Enclosure Management */
+#define	PCIZ_PL32	0x002a	/* Physical Layer 32.0 GT/s */
+#define	PCIZ_AP		0x002b	/* Alternate Protocol */
+#define	PCIZ_SFI	0x002c	/* System Firmware Intermediary */
 
 /* config registers for header type 0 devices */
 
@@ -334,6 +349,8 @@
 #define	PCIS_STORAGE_NVM	0x08
 #define	PCIP_STORAGE_NVM_NVMHCI_1_0	0x01
 #define	PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0	0x02
+#define	PCIS_STORAGE_UFS	0x09
+#define	PCIP_STORAGE_UFS_UFSHCI_1_0	0x01
 #define	PCIS_STORAGE_OTHER	0x80
 
 #define	PCIC_NETWORK	0x02
@@ -344,6 +361,8 @@
 #define	PCIS_NETWORK_ISDN	0x04
 #define	PCIS_NETWORK_WORLDFIP	0x05
 #define	PCIS_NETWORK_PICMG	0x06
+#define	PCIS_NETWORK_INFINIBAND	0x07
+#define	PCIS_NETWORK_HFC	0x08
 #define	PCIS_NETWORK_OTHER	0x80
 
 #define	PCIC_DISPLAY	0x03
@@ -357,6 +376,7 @@
 #define	PCIS_MULTIMEDIA_AUDIO	0x01
 #define	PCIS_MULTIMEDIA_TELE	0x02
 #define	PCIS_MULTIMEDIA_HDA	0x03
+#define	PCIP_MULTIMEDIA_HDA_VENDOR	0x01
 #define	PCIS_MULTIMEDIA_OTHER	0x80
 
 #define	PCIC_MEMORY	0x05
@@ -377,6 +397,8 @@
 #define	PCIS_BRIDGE_RACEWAY	0x08
 #define	PCIS_BRIDGE_PCI_TRANSPARENT 0x09
 #define	PCIS_BRIDGE_INFINIBAND	0x0a
+#define	PCIS_BRIDGE_AS_PCI	0x0b
+#define	PCIS_BRIDGE_AS_PCI_ASI_SIG	0x01
 #define	PCIS_BRIDGE_OTHER	0x80
 
 #define	PCIC_SIMPLECOMM	0x07
@@ -408,6 +430,7 @@
 #define	PCIS_BASEPERIPH_PCIHOT	0x04
 #define	PCIS_BASEPERIPH_SDHC	0x05
 #define	PCIS_BASEPERIPH_IOMMU	0x06
+#define	PCIS_BASEPERIPH_RCEC	0x07
 #define	PCIS_BASEPERIPH_OTHER	0x80
 
 #define	PCIC_INPUTDEV	0x09
@@ -450,6 +473,7 @@
 #define	PCIP_SERIALBUS_IPMI_BT		0x02
 #define	PCIS_SERIALBUS_SERCOS	0x08
 #define	PCIS_SERIALBUS_CANBUS	0x09
+#define	PCIS_SERIALBUS_MIPI_I3C	0x0a
 
 #define	PCIC_WIRELESS	0x0d
 #define	PCIS_WIRELESS_IRDA	0x00
@@ -459,6 +483,8 @@
 #define	PCIS_WIRELESS_BROADBAND	0x12
 #define	PCIS_WIRELESS_80211A	0x20
 #define	PCIS_WIRELESS_80211B	0x21
+#define	PCIS_WIRELESS_CELL	0x40
+#define	PCIS_WIRELESS_CELL_E	0x41
 #define	PCIS_WIRELESS_OTHER	0x80
 
 #define	PCIC_INTELLIIO	0x0e