svn commit: r325056 - head/sys/dev/ffec

[Ian Lepore]

Author: ian
Date: Sat Oct 28 17:30:49 2017
New Revision: 325056
URL: https://svnweb.freebsd.org/changeset/base/325056

Log:
  Avoid AXI bus issues due to a MAC reset on imx6sx and imx7.
  
  When the FEC is connected to the AXI bus (indicated by AVB flag), a
  MAC reset while a bus transaction is pending can hang the bus.
  Instead of resetting, turn off the ENABLE bit, which allows the
  hardware to complete any in-progress transfers (appending a bad CRC
  to any partial packet) and release the AXI bus.  This could probably
  be done unconditionally for all hardware variants, but that hasn't
  been tested.
  
  PR:		222634
  Submitted by:	sebastian.huber at embedded-brains.de

Modified:
  head/sys/dev/ffec/if_ffec.c

Modified: head/sys/dev/ffec/if_ffec.c
==============================================================================
--- head/sys/dev/ffec/if_ffec.c	Sat Oct 28 17:06:13 2017	(r325055)
+++ head/sys/dev/ffec/if_ffec.c	Sat Oct 28 17:30:49 2017	(r325056)
@@ -1639,8 +1639,21 @@ ffec_attach(device_t dev)
 	/* Try to get the MAC address from the hardware before resetting it. */
 	ffec_get_hwaddr(sc, eaddr);
 
-	/* Reset the hardware.  Disables all interrupts. */
-	WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
+	/*
+	 * Reset the hardware.  Disables all interrupts.
+	 *
+	 * When the FEC is connected to the AXI bus (indicated by AVB flag), a
+	 * MAC reset while a bus transaction is pending can hang the bus.
+	 * Instead of resetting, turn off the ENABLE bit, which allows the
+	 * hardware to complete any in-progress transfers (appending a bad CRC
+	 * to any partial packet) and release the AXI bus.  This could probably
+	 * be done unconditionally for all hardware variants, but that hasn't
+	 * been tested.
+	 */
+	if (sc->fectype & FECFLAG_AVB)
+		WR4(sc, FEC_ECR_REG, 0);
+	else
+		WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
 
 	/* Setup interrupt handler. */
 	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,