svn commit: r292735 - in head: . contrib/llvm/include/llvm-c contrib/llvm/include/llvm/CodeGen contrib/llvm/lib/CodeGen/AsmPrinter contrib/llvm/lib/CodeGen/SelectionDAG contrib/llvm/lib/IR contrib/...
Dimitry Andric
dim at FreeBSD.org
Fri Dec 25 21:39:50 UTC 2015
Author: dim
Date: Fri Dec 25 21:39:45 2015
New Revision: 292735
URL: https://svnweb.freebsd.org/changeset/base/292735
Log:
Upgrade our copies of clang and llvm to 3.7.1 release. This is a
bugfix-only release, with no new features.
Please note that from 3.5.0 onwards, clang and llvm require C++11
support to build; see UPDATING for more information.
Added:
head/contrib/llvm/patches/patch-08-clang-cc1as-dwarf2.diff
- copied unchanged from r292734, head/contrib/llvm/patches/patch-10-clang-cc1as-dwarf2.diff
Deleted:
head/contrib/llvm/patches/patch-08-llvm-r250085-fix-avx-crash.diff
head/contrib/llvm/patches/patch-09-clang-r250657-openmp.diff
head/contrib/llvm/patches/patch-10-clang-cc1as-dwarf2.diff
Modified:
head/ObsoleteFiles.inc
head/contrib/llvm/include/llvm-c/Core.h
head/contrib/llvm/include/llvm/CodeGen/CommandFlags.h
head/contrib/llvm/lib/CodeGen/AsmPrinter/WinException.cpp
head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
head/contrib/llvm/lib/IR/AsmWriter.cpp
head/contrib/llvm/lib/IR/Core.cpp
head/contrib/llvm/lib/LTO/LTOCodeGenerator.cpp
head/contrib/llvm/lib/MC/MCContext.cpp
head/contrib/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
head/contrib/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
head/contrib/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td
head/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
head/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h
head/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td
head/contrib/llvm/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
head/contrib/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
head/contrib/llvm/lib/Target/BPF/BPFISelLowering.cpp
head/contrib/llvm/lib/Target/BPF/BPFInstrInfo.td
head/contrib/llvm/lib/Target/BPF/BPFRegisterInfo.cpp
head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h
head/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td
head/contrib/llvm/lib/Target/PowerPC/PPCInstrQPX.td
head/contrib/llvm/lib/Target/PowerPC/PPCInstrVSX.td
head/contrib/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
head/contrib/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
head/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (contents, props changed)
head/contrib/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp
head/contrib/llvm/lib/Transforms/Scalar/GVN.cpp
head/contrib/llvm/lib/Transforms/Utils/Local.cpp
head/contrib/llvm/patches/README.TXT
head/contrib/llvm/tools/clang/lib/Basic/Targets.cpp
head/contrib/llvm/tools/clang/lib/Basic/Version.cpp
head/contrib/llvm/tools/clang/lib/CodeGen/CGCall.cpp
head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp
head/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp
head/contrib/llvm/tools/clang/lib/Sema/SemaExprCXX.cpp
head/contrib/llvm/tools/llvm-lto/llvm-lto.cpp
head/etc/mtree/BSD.debug.dist
head/etc/mtree/BSD.usr.dist
head/lib/clang/include/Makefile
head/lib/clang/include/clang/Basic/Version.inc
head/lib/clang/include/clang/Config/config.h
head/lib/clang/include/llvm/Config/config.h
head/lib/clang/include/llvm/Config/llvm-config.h
head/lib/libclang_rt/Makefile.inc
head/tools/build/mk/OptionalObsoleteFiles.inc
Directory Properties:
head/contrib/llvm/ (props changed)
head/contrib/llvm/tools/clang/ (props changed)
head/contrib/llvm/tools/llvm-dwarfdump/ (props changed)
head/contrib/llvm/tools/llvm-lto/ (props changed)
Modified: head/ObsoleteFiles.inc
==============================================================================
--- head/ObsoleteFiles.inc Fri Dec 25 18:11:40 2015 (r292734)
+++ head/ObsoleteFiles.inc Fri Dec 25 21:39:45 2015 (r292735)
@@ -38,6 +38,88 @@
# xargs -n1 | sort | uniq -d;
# done
+# 20151225: new clang import which bumps version from 3.7.0 to 3.7.1.
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/allocator_interface.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/asan_interface.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/common_interface_defs.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/coverage_interface.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/dfsan_interface.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/linux_syscall_hooks.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/lsan_interface.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/msan_interface.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/sanitizer/tsan_interface_atomic.h
+OLD_DIRS+=usr/lib/clang/3.7.0/include/sanitizer
+OLD_FILES+=usr/lib/clang/3.7.0/include/__stddef_max_align_t.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/__wmmintrin_aes.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/__wmmintrin_pclmul.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/adxintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/altivec.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/ammintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/arm_acle.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/arm_neon.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx2intrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512bwintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512cdintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512dqintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512erintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512fintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512vlbwintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512vldqintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avx512vlintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/avxintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/bmi2intrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/bmiintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/cpuid.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/cuda_builtin_vars.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/emmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/f16cintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/fma4intrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/fmaintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/fxsrintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/htmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/htmxlintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/ia32intrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/immintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/lzcntintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/mm3dnow.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/mm_malloc.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/mmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/module.modulemap
+OLD_FILES+=usr/lib/clang/3.7.0/include/nmmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/pmmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/popcntintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/prfchwintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/rdseedintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/rtmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/s390intrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/shaintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/smmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/tbmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/tmmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/vadefs.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/vecintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/wmmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/x86intrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/xmmintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/xopintrin.h
+OLD_FILES+=usr/lib/clang/3.7.0/include/xtestintrin.h
+OLD_DIRS+=usr/lib/clang/3.7.0/include
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.asan-i386.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.asan-x86_64.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.asan_cxx-i386.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.asan_cxx-x86_64.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.profile-arm.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.profile-i386.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.profile-x86_64.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.safestack-i386.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.safestack-x86_64.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.ubsan_standalone-i386.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.ubsan_standalone-x86_64.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-i386.a
+OLD_FILES+=usr/lib/clang/3.7.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-x86_64.a
+OLD_DIRS+=usr/lib/clang/3.7.0/lib/freebsd
+OLD_DIRS+=usr/lib/clang/3.7.0/lib
+OLD_DIRS+=usr/lib/clang/3.7.0
# 20151130: libelf moved from /usr/lib to /lib (libkvm dependency in r291406)
OLD_LIBS+=usr/lib/libelf.so.2
# 20151115: Fox bad upgrade scheme
Modified: head/contrib/llvm/include/llvm-c/Core.h
==============================================================================
--- head/contrib/llvm/include/llvm-c/Core.h Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/include/llvm-c/Core.h Fri Dec 25 21:39:45 2015 (r292735)
@@ -2675,7 +2675,8 @@ LLVMValueRef LLVMBuildInvoke(LLVMBuilder
LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
const char *Name);
LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
- unsigned NumClauses, const char *Name);
+ LLVMValueRef PersFn, unsigned NumClauses,
+ const char *Name);
LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn);
LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef);
Modified: head/contrib/llvm/include/llvm/CodeGen/CommandFlags.h
==============================================================================
--- head/contrib/llvm/include/llvm/CodeGen/CommandFlags.h Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/include/llvm/CodeGen/CommandFlags.h Fri Dec 25 21:39:45 2015 (r292735)
@@ -21,7 +21,7 @@
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCTargetOptionsCommandFlags.h"
-#include "llvm//MC/SubtargetFeature.h"
+#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Host.h"
Modified: head/contrib/llvm/lib/CodeGen/AsmPrinter/WinException.cpp
==============================================================================
--- head/contrib/llvm/lib/CodeGen/AsmPrinter/WinException.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/CodeGen/AsmPrinter/WinException.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -169,7 +169,7 @@ void WinException::endFunction(const Mac
Asm->OutStreamer->PopSection();
}
- if (shouldEmitMoves)
+ if (shouldEmitMoves || shouldEmitPersonality)
Asm->OutStreamer->EmitWinCFIEndProc();
}
Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
==============================================================================
--- head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -439,7 +439,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, Sele
ISD::ANY_EXTEND, dl, VT, Result);
ValResult = Result;
- ChainResult = Chain;
+ ChainResult = newLoad.getValue(1);
return;
}
Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
==============================================================================
--- head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -1010,6 +1010,8 @@ SDValue DAGTypeLegalizer::GetVectorEleme
// Calculate the element offset and add it to the pointer.
unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
+ assert(EltSize * 8 == EltVT.getSizeInBits() &&
+ "Converting bits to bytes lost precision");
Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
DAG.getConstant(EltSize, dl, Index.getValueType()));
Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
==============================================================================
--- head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -1528,9 +1528,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXT
if (CustomLowerNode(N, N->getValueType(0), true))
return SDValue();
- // Store the vector to the stack.
- EVT EltVT = VecVT.getVectorElementType();
+ // Make the vector elements byte-addressable if they aren't already.
SDLoc dl(N);
+ EVT EltVT = VecVT.getVectorElementType();
+ if (EltVT.getSizeInBits() < 8) {
+ SmallVector<SDValue, 4> ElementOps;
+ for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
+ ElementOps.push_back(DAG.getAnyExtOrTrunc(
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
+ DAG.getConstant(i, dl, MVT::i8)),
+ dl, MVT::i8));
+ }
+
+ EltVT = MVT::i8;
+ VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
+ VecVT.getVectorNumElements());
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
+ }
+
+ // Store the vector to the stack.
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
MachinePointerInfo(), false, false, 0);
Modified: head/contrib/llvm/lib/IR/AsmWriter.cpp
==============================================================================
--- head/contrib/llvm/lib/IR/AsmWriter.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/IR/AsmWriter.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -794,6 +794,10 @@ void SlotTracker::processFunction() {
ST_DEBUG("begin processFunction!\n");
fNext = 0;
+ // Process function metadata if it wasn't hit at the module-level.
+ if (!ShouldInitializeAllMetadata)
+ processFunctionMetadata(*TheFunction);
+
// Add all the function arguments with no names.
for(Function::const_arg_iterator AI = TheFunction->arg_begin(),
AE = TheFunction->arg_end(); AI != AE; ++AI)
@@ -807,8 +811,6 @@ void SlotTracker::processFunction() {
if (!BB.hasName())
CreateFunctionSlot(&BB);
- processFunctionMetadata(*TheFunction);
-
for (auto &I : BB) {
if (!I.getType()->isVoidTy() && !I.hasName())
CreateFunctionSlot(&I);
@@ -836,11 +838,11 @@ void SlotTracker::processFunction() {
void SlotTracker::processFunctionMetadata(const Function &F) {
SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
- for (auto &BB : F) {
- F.getAllMetadata(MDs);
- for (auto &MD : MDs)
- CreateMetadataSlot(MD.second);
+ F.getAllMetadata(MDs);
+ for (auto &MD : MDs)
+ CreateMetadataSlot(MD.second);
+ for (auto &BB : F) {
for (auto &I : BB)
processInstructionMetadata(I);
}
Modified: head/contrib/llvm/lib/IR/Core.cpp
==============================================================================
--- head/contrib/llvm/lib/IR/Core.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/IR/Core.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -2257,7 +2257,14 @@ LLVMValueRef LLVMBuildInvoke(LLVMBuilder
}
LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
- unsigned NumClauses, const char *Name) {
+ LLVMValueRef PersFn, unsigned NumClauses,
+ const char *Name) {
+ // The personality used to live on the landingpad instruction, but now it
+ // lives on the parent function. For compatibility, take the provided
+ // personality and put it on the parent function.
+ if (PersFn)
+ unwrap(B)->GetInsertBlock()->getParent()->setPersonalityFn(
+ cast<Function>(unwrap(PersFn)));
return wrap(unwrap(B)->CreateLandingPad(unwrap(Ty), NumClauses, Name));
}
Modified: head/contrib/llvm/lib/LTO/LTOCodeGenerator.cpp
==============================================================================
--- head/contrib/llvm/lib/LTO/LTOCodeGenerator.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/LTO/LTOCodeGenerator.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -63,14 +63,21 @@ const char* LTOCodeGenerator::getVersion
#endif
}
+static void handleLTODiagnostic(const DiagnosticInfo &DI) {
+ DiagnosticPrinterRawOStream DP(errs());
+ DI.print(DP);
+ errs() << "\n";
+}
+
LTOCodeGenerator::LTOCodeGenerator()
- : Context(getGlobalContext()), IRLinker(new Module("ld-temp.o", Context)) {
+ : Context(getGlobalContext()), IRLinker(new Module("ld-temp.o", Context),
+ handleLTODiagnostic) {
initializeLTOPasses();
}
LTOCodeGenerator::LTOCodeGenerator(std::unique_ptr<LLVMContext> Context)
: OwnedContext(std::move(Context)), Context(*OwnedContext),
- IRLinker(new Module("ld-temp.o", *OwnedContext)) {
+ IRLinker(new Module("ld-temp.o", *OwnedContext), handleLTODiagnostic) {
initializeLTOPasses();
}
Modified: head/contrib/llvm/lib/MC/MCContext.cpp
==============================================================================
--- head/contrib/llvm/lib/MC/MCContext.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/MC/MCContext.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -82,6 +82,7 @@ void MCContext::reset() {
UsedNames.clear();
Symbols.clear();
+ SectionSymbols.clear();
Allocator.Reset();
Instances.clear();
CompilationDir.clear();
Modified: head/contrib/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -264,6 +264,12 @@ void AMDGPUAsmPrinter::getSIProgramInfo(
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
// TODO: CodeSize should account for multiple functions.
+
+ // TODO: Should we count size of debug info?
+ if (MI.isDebugValue())
+ continue;
+
+ // FIXME: This is reporting 0 for many instructions.
CodeSize += MI.getDesc().Size;
unsigned numOperands = MI.getNumOperands();
Modified: head/contrib/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -134,13 +134,17 @@ static Value* GEPToVectorIndex(GetElemen
//
// TODO: Check isTriviallyVectorizable for calls and handle other
// instructions.
-static bool canVectorizeInst(Instruction *Inst) {
+static bool canVectorizeInst(Instruction *Inst, User *User) {
switch (Inst->getOpcode()) {
case Instruction::Load:
- case Instruction::Store:
case Instruction::BitCast:
case Instruction::AddrSpaceCast:
return true;
+ case Instruction::Store: {
+ // Must be the stored pointer operand, not a stored value.
+ StoreInst *SI = cast<StoreInst>(Inst);
+ return SI->getPointerOperand() == User;
+ }
default:
return false;
}
@@ -166,7 +170,7 @@ static bool tryPromoteAllocaToVector(All
for (User *AllocaUser : Alloca->users()) {
GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(AllocaUser);
if (!GEP) {
- if (!canVectorizeInst(cast<Instruction>(AllocaUser)))
+ if (!canVectorizeInst(cast<Instruction>(AllocaUser), Alloca))
return false;
WorkList.push_back(AllocaUser);
@@ -184,7 +188,7 @@ static bool tryPromoteAllocaToVector(All
GEPVectorIdx[GEP] = Index;
for (User *GEPUser : AllocaUser->users()) {
- if (!canVectorizeInst(cast<Instruction>(GEPUser)))
+ if (!canVectorizeInst(cast<Instruction>(GEPUser), AllocaUser))
return false;
WorkList.push_back(GEPUser);
@@ -240,7 +244,12 @@ static bool collectUsesWithPtrTypes(Valu
for (User *User : Val->users()) {
if(std::find(WorkList.begin(), WorkList.end(), User) != WorkList.end())
continue;
- if (isa<CallInst>(User)) {
+ if (CallInst *CI = dyn_cast<CallInst>(User)) {
+ // TODO: We might be able to handle some cases where the callee is a
+ // constantexpr bitcast of a function.
+ if (!CI->getCalledFunction())
+ return false;
+
WorkList.push_back(User);
continue;
}
@@ -250,6 +259,12 @@ static bool collectUsesWithPtrTypes(Valu
if (UseInst && UseInst->getOpcode() == Instruction::PtrToInt)
return false;
+ if (StoreInst *SI = dyn_cast_or_null<StoreInst>(UseInst)) {
+ // Reject if the stored value is not the pointer operand.
+ if (SI->getPointerOperand() != Val)
+ return false;
+ }
+
if (!User->getType()->isPointerTy())
continue;
Modified: head/contrib/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td Fri Dec 25 21:39:45 2015 (r292735)
@@ -14,8 +14,7 @@
let Namespace = "AMDGPU" in {
foreach Index = 0-15 in {
- // Indices are used in a variety of ways here, so don't set a size/offset.
- def sub#Index : SubRegIndex<-1, -1>;
+ def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
}
def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
Modified: head/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -71,12 +71,26 @@ void AMDGPUMCObjectWriter::writeObject(M
}
}
+static unsigned getFixupKindNumBytes(unsigned Kind) {
+ switch (Kind) {
+ case FK_Data_1:
+ return 1;
+ case FK_Data_2:
+ return 2;
+ case FK_Data_4:
+ return 4;
+ case FK_Data_8:
+ return 8;
+ default:
+ llvm_unreachable("Unknown fixup kind!");
+ }
+}
+
void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
unsigned DataSize, uint64_t Value,
bool IsPCRel) const {
switch ((unsigned)Fixup.getKind()) {
- default: llvm_unreachable("Unknown fixup kind");
case AMDGPU::fixup_si_sopp_br: {
uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
*Dst = (Value - 4) / 4;
@@ -96,6 +110,24 @@ void AMDGPUAsmBackend::applyFixup(const
*Dst = Value + 4;
break;
}
+ default: {
+ // FIXME: Copied from AArch64
+ unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
+ if (!Value)
+ return; // Doesn't change encoding.
+ MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
+
+ // Shift the value into position.
+ Value <<= Info.TargetOffset;
+
+ unsigned Offset = Fixup.getOffset();
+ assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
+
+ // For each byte of the fragment that the fixup touches, mask in the
+ // bits from the fixup value.
+ for (unsigned i = 0; i != NumBytes; ++i)
+ Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
+ }
}
}
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -157,6 +157,7 @@ SITargetLowering::SITargetLowering(Targe
setTruncStoreAction(MVT::i64, MVT::i32, Expand);
setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
+ setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
setOperationAction(ISD::LOAD, MVT::i1, Custom);
@@ -2252,10 +2253,8 @@ MachineSDNode *SITargetLowering::buildSc
SDValue Ptr) const {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
- uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
- 0xffffffff; // Size
- return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
+ return buildRSRC(DAG, DL, Ptr, 0, TII->getScratchRsrcWords23());
}
SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -2778,3 +2778,16 @@ uint64_t SIInstrInfo::getDefaultRsrcData
return RsrcDataFormat;
}
+
+uint64_t SIInstrInfo::getScratchRsrcWords23() const {
+ uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
+ AMDGPU::RSRC_TID_ENABLE |
+ 0xffffffff; // Size;
+
+ // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
+ // Clear them unless we want a huge stride.
+ if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
+ Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;
+
+ return Rsrc23;
+}
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h Fri Dec 25 21:39:45 2015 (r292735)
@@ -353,7 +353,7 @@ public:
}
uint64_t getDefaultRsrcDataFormat() const;
-
+ uint64_t getScratchRsrcWords23() const;
};
namespace AMDGPU {
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td Fri Dec 25 21:39:45 2015 (r292735)
@@ -1548,6 +1548,12 @@ defm V_WRITELANE_B32 : VOP2SI_3VI_m <
// These instructions only exist on SI and CI
let SubtargetPredicate = isSICI in {
+let isCommutable = 1 in {
+defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
+ VOP_F32_F32_F32
+>;
+} // End isCommutable = 1
+
defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
VOP_F32_F32_F32, AMDGPUfmin_legacy
>;
@@ -1562,12 +1568,6 @@ defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>
} // End isCommutable = 1
} // End let SubtargetPredicate = SICI
-let isCommutable = 1 in {
-defm V_MAC_LEGACY_F32 : VOP2_VI3_Inst <vop23<0x6, 0x28e>, "v_mac_legacy_f32",
- VOP_F32_F32_F32
->;
-} // End isCommutable = 1
-
defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
VOP_I32_I32_I32
>;
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -135,8 +135,7 @@ bool SIPrepareScratchRegs::runOnMachineF
unsigned ScratchRsrcReg =
RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
- uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
- 0xffffffff; // Size
+ uint64_t Rsrc23 = TII->getScratchRsrcWords23();
unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
@@ -152,11 +151,11 @@ bool SIPrepareScratchRegs::runOnMachineF
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
- .addImm(Rsrc & 0xffffffff)
+ .addImm(Rsrc23 & 0xffffffff)
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
- .addImm(Rsrc >> 32)
+ .addImm(Rsrc23 >> 32)
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
// Scratch Offset
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -26,23 +26,25 @@ using namespace llvm;
SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}
-BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(AMDGPU::EXEC);
+void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
+ MCRegAliasIterator R(Reg, this, true);
- // EXEC_LO and EXEC_HI could be allocated and used as regular register,
- // but this seems likely to result in bugs, so I'm marking them as reserved.
- Reserved.set(AMDGPU::EXEC_LO);
- Reserved.set(AMDGPU::EXEC_HI);
+ for (; R.isValid(); ++R)
+ Reserved.set(*R);
+}
+BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
- Reserved.set(AMDGPU::FLAT_SCR);
- Reserved.set(AMDGPU::FLAT_SCR_LO);
- Reserved.set(AMDGPU::FLAT_SCR_HI);
+
+ // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
+ // this seems likely to result in bugs, so I'm marking them as reserved.
+ reserveRegisterTuples(Reserved, AMDGPU::EXEC);
+ reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
// Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
- Reserved.set(AMDGPU::VGPR255);
- Reserved.set(AMDGPU::VGPR254);
+ reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
+ reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
// Tonga and Iceland can only allocate a fixed number of SGPRs due
// to a hw bug.
@@ -54,10 +56,7 @@ BitVector SIRegisterInfo::getReservedReg
for (unsigned i = Limit; i < NumSGPRs; ++i) {
unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
- MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
-
- for (; R.isValid(); ++R)
- Reserved.set(*R);
+ reserveRegisterTuples(Reserved, Reg);
}
}
Modified: head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
==============================================================================
--- head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h Fri Dec 25 21:39:45 2015 (r292735)
@@ -23,7 +23,10 @@
namespace llvm {
struct SIRegisterInfo : public AMDGPURegisterInfo {
+private:
+ void reserveRegisterTuples(BitVector &, unsigned Reg) const;
+public:
SIRegisterInfo();
BitVector getReservedRegs(const MachineFunction &MF) const override;
Modified: head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -15,6 +15,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
@@ -9104,6 +9105,10 @@ bool ARMAsmParser::parseDirectiveArch(SM
return false;
}
+ Triple T;
+ STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
+ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+
getTargetStreamer().emitArch(ID);
return false;
}
Modified: head/contrib/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -50,6 +50,7 @@ private:
// Complex Pattern for address selection.
bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
+ bool SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
};
}
@@ -67,7 +68,7 @@ bool BPFDAGToDAGISel::SelectAddr(SDValue
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false;
- // Addresses of the form FI+const or FI|const
+ // Addresses of the form Addr+const or Addr|const
if (CurDAG->isBaseWithConstantOffset(Addr)) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
if (isInt<32>(CN->getSExtValue())) {
@@ -89,6 +90,31 @@ bool BPFDAGToDAGISel::SelectAddr(SDValue
return true;
}
+// ComplexPattern used on BPF FI instruction
+bool BPFDAGToDAGISel::SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ SDLoc DL(Addr);
+
+ if (!CurDAG->isBaseWithConstantOffset(Addr))
+ return false;
+
+ // Addresses of the form Addr+const or Addr|const
+ ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+ if (isInt<32>(CN->getSExtValue())) {
+
+ // If the first operand is a FI, get the TargetFI Node
+ if (FrameIndexSDNode *FIN =
+ dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
+ else
+ return false;
+
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
+ return true;
+ }
+
+ return false;
+}
+
SDNode *BPFDAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode = Node->getOpcode();
@@ -104,13 +130,6 @@ SDNode *BPFDAGToDAGISel::Select(SDNode *
// tablegen selection should be handled here.
switch (Opcode) {
default: break;
-
- case ISD::UNDEF: {
- errs() << "BUG: "; Node->dump(CurDAG); errs() << '\n';
- report_fatal_error("shouldn't see UNDEF during Select");
- break;
- }
-
case ISD::INTRINSIC_W_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
switch (IntNo) {
Modified: head/contrib/llvm/lib/Target/BPF/BPFISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/BPF/BPFISelLowering.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/BPF/BPFISelLowering.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -102,6 +102,7 @@ BPFTargetLowering::BPFTargetLowering(con
setOperationAction(ISD::BR_CC, MVT::i64, Custom);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::SETCC, MVT::i64, Expand);
setOperationAction(ISD::SELECT, MVT::i64, Expand);
@@ -128,9 +129,6 @@ BPFTargetLowering::BPFTargetLowering(con
setOperationAction(ISD::SUBC, MVT::i64, Expand);
setOperationAction(ISD::SUBE, MVT::i64, Expand);
- // no UNDEF allowed
- setOperationAction(ISD::UNDEF, MVT::i64, Expand);
-
setOperationAction(ISD::ROTR, MVT::i64, Expand);
setOperationAction(ISD::ROTL, MVT::i64, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
Modified: head/contrib/llvm/lib/Target/BPF/BPFInstrInfo.td
==============================================================================
--- head/contrib/llvm/lib/Target/BPF/BPFInstrInfo.td Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/BPF/BPFInstrInfo.td Fri Dec 25 21:39:45 2015 (r292735)
@@ -54,7 +54,8 @@ def i64immSExt32 : PatLeaf<(imm),
[{return isInt<32>(N->getSExtValue()); }]>;
// Addressing modes.
-def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [frameindex], []>;
+def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
+def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
// Address operands
def MEMri : Operand<i64> {
@@ -260,6 +261,15 @@ def MOV_rr : MOV_RR<"mov">;
def MOV_ri : MOV_RI<"mov">;
}
+def FI_ri
+ : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
+ "lea\t$dst, $addr",
+ [(set i64:$dst, FIri:$addr)]> {
+ // This is a tentative instruction, and will be replaced
+ // with MOV_rr and ADD_ri in PEI phase
+}
+
+
def LD_pseudo
: InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
"ld_pseudo\t$dst, $pseudo, $imm",
Modified: head/contrib/llvm/lib/Target/BPF/BPFRegisterInfo.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/BPF/BPFRegisterInfo.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/BPF/BPFRegisterInfo.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -58,14 +58,13 @@ void BPFRegisterInfo::eliminateFrameInde
unsigned FrameReg = getFrameRegister(MF);
int FrameIndex = MI.getOperand(i).getIndex();
+ const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
+ MachineBasicBlock &MBB = *MI.getParent();
if (MI.getOpcode() == BPF::MOV_rr) {
- const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
MI.getOperand(i).ChangeToRegister(FrameReg, false);
-
- MachineBasicBlock &MBB = *MI.getParent();
unsigned reg = MI.getOperand(i - 1).getReg();
BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
.addReg(reg)
@@ -79,8 +78,24 @@ void BPFRegisterInfo::eliminateFrameInde
if (!isInt<32>(Offset))
llvm_unreachable("bug in frame offset");
- MI.getOperand(i).ChangeToRegister(FrameReg, false);
- MI.getOperand(i + 1).ChangeToImmediate(Offset);
+ if (MI.getOpcode() == BPF::FI_ri) {
+ // architecture does not really support FI_ri, replace it with
+ // MOV_rr <target_reg>, frame_reg
+ // ADD_ri <target_reg>, imm
+ unsigned reg = MI.getOperand(i - 1).getReg();
+
+ BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
+ .addReg(FrameReg);
+ BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
+ .addReg(reg)
+ .addImm(Offset);
+
+ // Remove FI_ri instruction
+ MI.eraseFromParent();
+ } else {
+ MI.getOperand(i).ChangeToRegister(FrameReg, false);
+ MI.getOperand(i + 1).ChangeToImmediate(Offset);
+ }
}
unsigned BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Modified: head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h
==============================================================================
--- head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h Fri Dec 25 21:39:45 2015 (r292735)
@@ -269,6 +269,14 @@ namespace llvm {
unsigned getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override;
+ /// Returns true if a cast between SrcAS and DestAS is a noop.
+ bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+ // Mips doesn't have any special address spaces so we just reserve
+ // the first 256 for software use (e.g. OpenCL) and treat casts
+ // between them as noops.
+ return SrcAS < 256 && DestAS < 256;
+ }
+
protected:
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
Modified: head/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -115,6 +115,11 @@ bool MipsSEDAGToDAGISel::replaceUsesWith
if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
continue;
+ // Also, we have to check that the register class of the operand
+ // contains the zero register.
+ if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
+ continue;
+
MO.setReg(ZeroReg);
}
Modified: head/contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -947,11 +947,11 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDISdtprelHA:
- // Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
- // Into: %Xd = ADDIS8 %X3, sym at dtprel@ha
+ // Transform: %Xd = ADDISdtprelHA %Xs, <ga:@sym>
+ // Into: %Xd = ADDIS8 %Xs, sym at dtprel@ha
case PPC::ADDISdtprelHA32: {
- // Transform: %Rd = ADDISdtprelHA32 %R3, <ga:@sym>
- // Into: %Rd = ADDIS %R3, sym at dtprel@ha
+ // Transform: %Rd = ADDISdtprelHA32 %Rs, <ga:@sym>
+ // Into: %Rd = ADDIS %Rs, sym at dtprel@ha
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -962,7 +962,7 @@ void PPCAsmPrinter::EmitInstruction(cons
*OutStreamer,
MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
.addReg(MI->getOperand(0).getReg())
- .addReg(Subtarget->isPPC64() ? PPC::X3 : PPC::R3)
+ .addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
return;
}
Modified: head/contrib/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -197,10 +197,18 @@ static bool isLargeIntegerTy(bool Is32Bi
// Determining the address of a TLS variable results in a function call in
// certain TLS models.
static bool memAddrUsesCTR(const PPCTargetMachine *TM,
- const llvm::Value *MemAddr) {
+ const Value *MemAddr) {
const auto *GV = dyn_cast<GlobalValue>(MemAddr);
- if (!GV)
+ if (!GV) {
+ // Recurse to check for constants that refer to TLS global variables.
+ if (const auto *CV = dyn_cast<Constant>(MemAddr))
+ for (const auto &CO : CV->operands())
+ if (memAddrUsesCTR(TM, CO))
+ return true;
+
return false;
+ }
+
if (!GV->isThreadLocal())
return false;
if (!TM)
@@ -239,6 +247,11 @@ bool PPCCTRLoops::mightUseCTR(const Trip
if (F->getIntrinsicID() != Intrinsic::not_intrinsic) {
switch (F->getIntrinsicID()) {
default: continue;
+ // If we have a call to ppc_is_decremented_ctr_nonzero, or ppc_mtctr
+ // we're definitely using CTR.
+ case Intrinsic::ppc_is_decremented_ctr_nonzero:
+ case Intrinsic::ppc_mtctr:
+ return true;
// VisualStudio defines setjmp as _setjmp
#if defined(_MSC_VER) && defined(setjmp) && \
@@ -426,6 +439,7 @@ bool PPCCTRLoops::convertToCTRLoop(Loop
// Process nested loops first.
for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
MadeChange |= convertToCTRLoop(*I);
+ DEBUG(dbgs() << "Nested loop converted\n");
}
// If a nested loop has been converted, then we can't convert this loop.
Modified: head/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -2570,13 +2570,25 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *
return nullptr;
}
// ISD::OR doesn't get all the bitfield insertion fun.
- // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
+ // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
+ // bitfield insert.
if (isInt32Immediate(N->getOperand(1), Imm) &&
N->getOperand(0).getOpcode() == ISD::OR &&
isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
+ // The idea here is to check whether this is equivalent to:
+ // (c1 & m) | (x & ~m)
+ // where m is a run-of-ones mask. The logic here is that, for each bit in
+ // c1 and c2:
+ // - if both are 1, then the output will be 1.
+ // - if both are 0, then the output will be 0.
+ // - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
+ // come from x.
+ // - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
+ // be 0.
+ // If that last condition is never the case, then we can form m from the
+ // bits that are the same between c1 and c2.
unsigned MB, ME;
- Imm = ~(Imm^Imm2);
- if (isRunOfOnes(Imm, MB, ME)) {
+ if (isRunOfOnes(~(Imm^Imm2), MB, ME) && !(~Imm & Imm2)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0, dl), getI32Imm(MB, dl),
@@ -2787,6 +2799,8 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *
SDValue Base, Offset;
if (LD->isUnindexed() &&
+ (LD->getMemoryVT() == MVT::f64 ||
+ LD->getMemoryVT() == MVT::i64) &&
SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
SDValue Chain = LD->getChain();
SDValue Ops[] = { Base, Offset, Chain };
Modified: head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -431,6 +431,8 @@ PPCTargetLowering::PPCTargetLowering(con
AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
setOperationAction(ISD::SELECT, VT, Promote);
AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
+ setOperationAction(ISD::SELECT_CC, VT, Promote);
+ AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
setOperationAction(ISD::STORE, VT, Promote);
AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
@@ -7175,7 +7177,6 @@ SDValue PPCTargetLowering::LowerVECTOR_S
PPC::isSplatShuffleMask(SVOp, 4) ||
PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
- PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
@@ -7183,8 +7184,10 @@ SDValue PPCTargetLowering::LowerVECTOR_S
PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
+ (Subtarget.hasP8Altivec() && (
+ PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
return Op;
}
}
@@ -7195,7 +7198,6 @@ SDValue PPCTargetLowering::LowerVECTOR_S
unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
- PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
@@ -7203,8 +7205,10 @@ SDValue PPCTargetLowering::LowerVECTOR_S
PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
+ (Subtarget.hasP8Altivec() && (
+ PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
return Op;
// Check to see if this is a shuffle of 4-byte values. If so, we can use our
Modified: head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Dec 25 21:39:45 2015 (r292735)
@@ -309,6 +309,11 @@ PPCInstrInfo::commuteInstruction(Machine
unsigned MB = MI->getOperand(4).getImm();
unsigned ME = MI->getOperand(5).getImm();
+ // We can't commute a trivial mask (there is no way to represent an all-zero
+ // mask).
+ if (MB == 0 && ME == 31)
+ return nullptr;
+
if (NewMI) {
// Create a new instruction.
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
Modified: head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td
==============================================================================
--- head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Dec 25 18:11:40 2015 (r292734)
+++ head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Dec 25 21:39:45 2015 (r292735)
@@ -2835,24 +2835,84 @@ def : Pat<(i64 (anyext i1:$in)),
(SELECT_I8 $in, (LI8 1), (LI8 0))>;
// match setcc on i1 variables.
+// CRANDC is:
+// 1 1 : F
+// 1 0 : T
+// 0 1 : F
+// 0 0 : F
+//
+// LT is:
+// -1 -1 : F
+// -1 0 : T
+// 0 -1 : F
+// 0 0 : F
+//
+// ULT is:
+// 1 1 : F
+// 1 0 : F
+// 0 1 : T
+// 0 0 : F
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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