svn commit: r292692 - in head/sys: conf mips/include

[Adrian Chadd]

Author: adrian
Date: Thu Dec 24 15:52:21 2015
New Revision: 292692
URL: https://svnweb.freebsd.org/changeset/base/292692

Log:
  Begin the initial support for the mips1004kc core.
  
  * add build option;
  * add initial coherence manager config register bits;
  * use the right hazard instruction (ehb);
  * add page attributes.
  
  Tested:
  
  * MT7621A SoC (not yet in-tree)
  
  Submitted by:	Stanislav Galabov <sgalabov at gmail.com>

Modified:
  head/sys/conf/options.mips
  head/sys/mips/include/cpufunc.h
  head/sys/mips/include/cpuregs.h

Modified: head/sys/conf/options.mips
==============================================================================
--- head/sys/conf/options.mips	Thu Dec 24 15:47:51 2015	(r292691)
+++ head/sys/conf/options.mips	Thu Dec 24 15:52:21 2015	(r292692)
@@ -31,6 +31,7 @@
 CPU_MIPS4KC	opt_global.h
 CPU_MIPS24KC	opt_global.h
 CPU_MIPS74KC	opt_global.h
+CPU_MIPS1004KC	opt_global.h
 CPU_MIPS32	opt_global.h
 CPU_MIPS64	opt_global.h
 CPU_SENTRY5	opt_global.h

Modified: head/sys/mips/include/cpufunc.h
==============================================================================
--- head/sys/mips/include/cpufunc.h	Thu Dec 24 15:47:51 2015	(r292691)
+++ head/sys/mips/include/cpufunc.h	Thu Dec 24 15:52:21 2015	(r292692)
@@ -248,7 +248,7 @@ MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_C
 #if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
 MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
 #endif
-#ifdef CPU_NLM
+#if defined(CPU_NLM) || defined(CPU_MIPS1004KC)
 MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
 #endif
 MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
@@ -259,6 +259,7 @@ MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
 MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
 #endif
 MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
+MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3);
 
 /* XXX: Some of these registers are specific to MIPS32. */
 #if !defined(__mips_n64)

Modified: head/sys/mips/include/cpuregs.h
==============================================================================
--- head/sys/mips/include/cpuregs.h	Thu Dec 24 15:47:51 2015	(r292691)
+++ head/sys/mips/include/cpuregs.h	Thu Dec 24 15:52:21 2015	(r292692)
@@ -154,6 +154,11 @@
 #define	MIPS_CCA_CACHED		0x03
 #endif
 
+#if defined(CPU_MIPS1004KC)
+#define	MIPS_CCA_UNCACHED	0x02
+#define	MIPS_CCA_CACHED		0x05
+#endif
+
 #ifndef	MIPS_CCA_UNCACHED
 #define	MIPS_CCA_UNCACHED	MIPS_CCA_UC
 #endif
@@ -209,7 +214,7 @@
 #define	COP0_SYNC	.word 0xc0	/* ehb */
 #elif defined(CPU_SB1)
 #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
-#elif defined(CPU_MIPS74KC)
+#elif defined(CPU_MIPS74KC) || defined(CPU_MIPS1004KC)
 #define	COP0_SYNC	 .word 0xc0	/* ehb */
 #else
 /*
@@ -557,6 +562,8 @@
 #define MIPS_CONFIG2_SS_SHIFT		8		/* Secondary cache sets per way */
 #define MIPS_CONFIG2_SS_MASK		0xf
 
+#define MIPS_CONFIG3_CMGCR_MASK		(1 << 29)	/* Coherence manager present */
+
 #define MIPS_CONFIG4_MMUSIZEEXT		0x000000FF	/* bits 7.. 0 MMU Size Extension */
 #define MIPS_CONFIG4_MMUEXTDEF		0x0000C000	/* bits 15.14 MMU Extension Definition */
 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT	0x00004000 /* This values denotes CONFIG4 bits  */
@@ -634,4 +641,8 @@
 #define	MIPS_OPCODE_SHIFT	26
 #define	MIPS_OPCODE_C1		0x11
 
+/* Coherence manager constants */
+#define	MIPS_CMGCRB_BASE	11
+#define	MIPS_CMGCRF_BASE	(~((1 << MIPS_CMGCRB_BASE) - 1))
+
 #endif /* _MIPS_CPUREGS_H_ */