svn commit: r292526 - head/sys/mips/mips

[Adrian Chadd]

Author: adrian
Date: Mon Dec 21 01:48:16 2015
New Revision: 292526
URL: https://svnweb.freebsd.org/changeset/base/292526

Log:
  [mips] print out l2 cache configuration if it exists.
  
  The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board
  has an L2 cache:
  
  Cache info:
    picache_stride    = 4096
    picache_loopcount = 8
    pdcache_stride    = 4096
    pdcache_loopcount = 8
  cpu0: Ingenic Xburst processor v79.2
    MMU: Standard TLB, 32 entries
    L1 i-cache: 8 ways of 128 sets, 32 bytes per line
    L1 d-cache: 8 ways of 128 sets, 32 bytes per line
    L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size
    Config1=0xbe67338b<WatchRegs,EJTAG,FPU>
    Config2=0x80000267
    Config3=0x20

Modified:
  head/sys/mips/mips/cpu.c

Modified: head/sys/mips/mips/cpu.c
==============================================================================
--- head/sys/mips/mips/cpu.c	Mon Dec 21 01:14:54 2015	(r292525)
+++ head/sys/mips/mips/cpu.c	Mon Dec 21 01:48:16 2015	(r292526)
@@ -318,6 +318,18 @@ cpu_identify(void)
 		    cpuinfo.l1.dc_nsets, cpuinfo.l1.dc_linesize);
 	}
 
+	printf("  L2 cache: ");
+	if (cpuinfo.l2.dc_linesize == 0) {
+		printf("disabled");
+	} else {
+		printf("%d ways of %d sets, %d bytes per line, "
+		    "%d KiB total size\n",
+		    cpuinfo.l2.dc_nways,
+		    cpuinfo.l2.dc_nsets,
+		    cpuinfo.l2.dc_linesize,
+		    cpuinfo.l2.dc_size / 1024);
+	}
+
 	cfg0 = mips_rd_config();
 	/* If config register selection 1 does not exist, exit. */
 	if (!(cfg0 & MIPS_CONFIG_CM))
@@ -335,6 +347,7 @@ cpu_identify(void)
 	 * Config2 contains no useful information other then Config3 
 	 * existence flag
 	 */
+	printf("  Config2=0x%08x\n", cfg2);
 
 	/* If config register selection 3 does not exist, exit. */
 	if (!(cfg2 & MIPS_CONFIG_CM))