svn commit: r262411 - head/sys/arm/arm

[Konstantin Belousov]

On Sun, Feb 23, 2014 at 10:52:48PM +0000, Ian Lepore wrote:
> Author: ian
> Date: Sun Feb 23 22:52:48 2014
> New Revision: 262411
> URL: http://svnweb.freebsd.org/changeset/base/262411
> 
> Log:
>   If the L2 cache type is PIPT, pass a physical address for a flush.
>   
>   While this is technically more correct, I don't think it much matters,
>   because the only thing in the tree that calls cpu_flush_dcache() is md(4)
>   and I'm > 99% sure it's bogus that it does so; md has no ability to do
>   anything that can perturb data cache coherency.

Yes, md(4) does not break data cache coherency, but I think that
Marcel added the flush to ensure instruction cache coherency.  The
intent was to ensure that harward-architecture machines would
see up-to-date memory content when fetching instructions after
read on md(4).
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