svn commit: r249123 - head/sys/mips/atheros

[Adrian Chadd]

Author: adrian
Date: Fri Apr  5 01:35:59 2013
New Revision: 249123
URL: http://svnweb.freebsd.org/changeset/base/249123

Log:
  Implement the AR933x ethernet support.
  
  Obtained from:	OpenWRT

Modified:
  head/sys/mips/atheros/ar933x_chip.c
  head/sys/mips/atheros/ar933xreg.h
  head/sys/mips/atheros/if_arge.c

Modified: head/sys/mips/atheros/ar933x_chip.c
==============================================================================
--- head/sys/mips/atheros/ar933x_chip.c	Fri Apr  5 00:57:10 2013	(r249122)
+++ head/sys/mips/atheros/ar933x_chip.c	Fri Apr  5 01:35:59 2013	(r249123)
@@ -200,8 +200,23 @@ ar933x_chip_ddr_flush_ip2(void)
 static uint32_t
 ar933x_chip_get_eth_pll(unsigned int mac, int speed)
 {
+	uint32_t pll;
 
-	return (0);
+	switch (speed) {
+	case 10:
+		pll = AR933X_PLL_VAL_10;
+		break;
+	case 100:
+		pll = AR933X_PLL_VAL_100;
+		break;
+	case 1000:
+		pll = AR933X_PLL_VAL_1000;
+		break;
+	default:
+		printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+		pll = 0;
+	}
+	return (pll);
 }
 
 static void

Modified: head/sys/mips/atheros/ar933xreg.h
==============================================================================
--- head/sys/mips/atheros/ar933xreg.h	Fri Apr  5 00:57:10 2013	(r249122)
+++ head/sys/mips/atheros/ar933xreg.h	Fri Apr  5 01:35:59 2013	(r249123)
@@ -75,4 +75,8 @@
 
 #define	AR933X_BOOTSTRAP_REF_CLK_40		(1 << 0)
 
+#define	AR933X_PLL_VAL_1000			0x00110000
+#define	AR933X_PLL_VAL_100			0x00001099
+#define	AR933X_PLL_VAL_10			0x00991099
+
 #endif	/* __AR93XX_REG_H__ */

Modified: head/sys/mips/atheros/if_arge.c
==============================================================================
--- head/sys/mips/atheros/if_arge.c	Fri Apr  5 00:57:10 2013	(r249122)
+++ head/sys/mips/atheros/if_arge.c	Fri Apr  5 01:35:59 2013	(r249123)
@@ -572,6 +572,8 @@ arge_attach(device_t dev)
 		case AR71XX_SOC_AR7240:
 		case AR71XX_SOC_AR7241:
 		case AR71XX_SOC_AR7242:
+		case AR71XX_SOC_AR9330:
+		case AR71XX_SOC_AR9331:
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
 			break;
@@ -899,6 +901,8 @@ arge_set_pll(struct arge_softc *sc, int 
 		case AR71XX_SOC_AR7240:
 		case AR71XX_SOC_AR7241:
 		case AR71XX_SOC_AR7242:
+		case AR71XX_SOC_AR9330:
+		case AR71XX_SOC_AR9331:
 			fifo_tx = 0x01f00140;
 			break;
 		case AR71XX_SOC_AR9130: