svn commit: r238861 - head/sys/mips/mips

[Robert Watson]

Author: rwatson
Date: Sat Jul 28 11:09:03 2012
New Revision: 238861
URL: http://svn.freebsd.org/changeset/base/238861

Log:
  Merge FreeBSD/beri Perforce change @211945 to head:
  
  Modify MIPS page table entry (PTE) initialisation so that cachability
  bits are set only once, using is_cacheable_mem() to determine what
  caching properties are required, rather than also unconditionally
  setting PTE_C_CACHE in init_pte_prot().  As PTE_C_CACHE |
  PTE_C_UNCACHED == PTE_C_CACHE, this meant that all userspace memory
  mappings of device memory (incorrectly) used caching TLB entries.
  
  This is arguably not quite what we want, even though it is (more)
  consistent with the MIPS pmap design: PTE caching properties should
  be derived from machine-independent page table attributes, but this
  is a substantially more complex change as the MIPS pmap doesn't yet
  know about page attributes, causing it to ignore requests by device
  drivers that want uncached userspace memory mappings as they
  describe memory-mapped FIFOs or shared memory with a device not
  participating in the cache coherence scheme.
  
  This fixes cacheability issues (specifically, undesired and
  unrequested caching) seen in userspace memory mappings of Avalon SoC
  bus device memory on BERI MIPS.
  
  Discussed with:	jmallett, alc
  Sponsored by:	DARPA, AFRL
  MFC after:	3 days

Modified:
  head/sys/mips/mips/pmap.c

Modified: head/sys/mips/mips/pmap.c
==============================================================================
--- head/sys/mips/mips/pmap.c	Sat Jul 28 07:56:23 2012	(r238860)
+++ head/sys/mips/mips/pmap.c	Sat Jul 28 11:09:03 2012	(r238861)
@@ -3146,16 +3146,16 @@ init_pte_prot(vm_offset_t va, vm_page_t 
 	pt_entry_t rw;
 
 	if (!(prot & VM_PROT_WRITE))
-		rw =  PTE_V | PTE_RO | PTE_C_CACHE;
+		rw =  PTE_V | PTE_RO;
 	else if ((m->oflags & VPO_UNMANAGED) == 0) {
 		if ((m->md.pv_flags & PV_TABLE_MOD) != 0)
-			rw =  PTE_V | PTE_D | PTE_C_CACHE;
+			rw =  PTE_V | PTE_D;
 		else
-			rw = PTE_V | PTE_C_CACHE;
+			rw = PTE_V;
 		vm_page_aflag_set(m, PGA_WRITEABLE);
 	} else
 		/* Needn't emulate a modified bit for unmanaged pages. */
-		rw =  PTE_V | PTE_D | PTE_C_CACHE;
+		rw =  PTE_V | PTE_D;
 	return (rw);
 }