svn commit: r238551 - head/sys/dev/usb/controller

[Alexander Motin]

Author: mav
Date: Tue Jul 17 14:03:04 2012
New Revision: 238551
URL: http://svn.freebsd.org/changeset/base/238551

Log:
  For Intel Panther/Lynx Point USB 3.0 xHCI controllers enable SuperSpeed USB
  capability and reroute USB 2.0 ports to the xHCI controller.
  
  Reviewed by:	hselasky

Modified:
  head/sys/dev/usb/controller/xhci_pci.c
  head/sys/dev/usb/controller/xhcireg.h

Modified: head/sys/dev/usb/controller/xhci_pci.c
==============================================================================
--- head/sys/dev/usb/controller/xhci_pci.c	Tue Jul 17 13:03:47 2012	(r238550)
+++ head/sys/dev/usb/controller/xhci_pci.c	Tue Jul 17 14:03:04 2012	(r238551)
@@ -101,6 +101,8 @@ xhci_pci_match(device_t self)
 
 	case 0x1e318086:
 		return ("Intel Panther Point USB 3.0 controller");
+	case 0x8c318086:
+		return ("Intel Lynx Point USB 3.0 controller");
 
 	default:
 		break;
@@ -245,6 +247,7 @@ static int
 xhci_pci_take_controller(device_t self)
 {
 	struct xhci_softc *sc = device_get_softc(self);
+	uint32_t device_id = pci_get_devid(self);
 	uint32_t cparams;
 	uint32_t eecp;
 	uint32_t eec;
@@ -285,5 +288,13 @@ xhci_pci_take_controller(device_t self)
 			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
 		}
 	}
+
+	/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
+	if (device_id == 0x1e318086 /* Panther Point */ ||
+	    device_id == 0x8c318086 /* Lynx Point */) {
+		pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 0xffffffff, 4);
+		pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, 0xffffffff, 4);
+	}
+
 	return (0);
 }

Modified: head/sys/dev/usb/controller/xhcireg.h
==============================================================================
--- head/sys/dev/usb/controller/xhcireg.h	Tue Jul 17 13:03:47 2012	(r238550)
+++ head/sys/dev/usb/controller/xhcireg.h	Tue Jul 17 14:03:04 2012	(r238551)
@@ -34,6 +34,9 @@
 #define	PCI_USB_REV_3_0		0x30	/* USB 3.0 */
 #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */
 
+#define	PCI_XHCI_INTEL_XUSB2PR	0xD0	/* Intel USB2 Port Routing */
+#define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8	/* Intel USB3 Port SuperSpeed Enable */
+
 /* XHCI capability registers */
 #define	XHCI_CAPLENGTH		0x00	/* RO capability */
 #define	XHCI_RESERVED		0x01	/* Reserved */