svn commit: r224072 - head/sys/mips/malta

[Adrian Chadd]

Author: adrian
Date: Sat Jul 16 00:30:23 2011
New Revision: 224072
URL: http://svn.freebsd.org/changeset/base/224072

Log:
  The i8259 controller is initialized incorrectly on MALTA.  It writes
  mask bits to control register and control bits to mask register.
  
  The former causes ICW1_RESET|ICW1_LTIM combination to be written to
  control register, which on QEMU results in "level sensitive irq not
  supported" error.
  
  Submitted by:	Robert Millan <rmh at debian.org>

Modified:
  head/sys/mips/malta/gt_pci.c

Modified: head/sys/mips/malta/gt_pci.c
==============================================================================
--- head/sys/mips/malta/gt_pci.c	Fri Jul 15 21:37:13 2011	(r224071)
+++ head/sys/mips/malta/gt_pci.c	Sat Jul 16 00:30:23 2011	(r224072)
@@ -326,15 +326,15 @@ gt_pci_attach(device_t dev)
 	    ICW4_8086);
 
 	/* mask all interrupts */
-	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
 	    sc->sc_imask & 0xff);
 
 	/* enable special mask mode */
-	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
 	    OCW3_SEL | OCW3_ESMM | OCW3_SMM);
 
 	/* read IRR by default */
-	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
 	    OCW3_SEL | OCW3_RR);
 
 	/* reset, program device, 4 bytes */
@@ -348,15 +348,15 @@ gt_pci_attach(device_t dev)
 	    ICW4_8086);
 
 	/* mask all interrupts */
-	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
 	    sc->sc_imask & 0xff);
 
 	/* enable special mask mode */
-	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
 	    OCW3_SEL | OCW3_ESMM | OCW3_SMM);
 
 	/* read IRR by default */
-	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
 	    OCW3_SEL | OCW3_RR);
 
 	/*