svn commit: r220990 - head/sys/dev/ath/ath_hal/ar5416
Adrian Chadd
adrian at FreeBSD.org
Sun Apr 24 15:53:58 UTC 2011
Author: adrian
Date: Sun Apr 24 15:53:57 2011
New Revision: 220990
URL: http://svn.freebsd.org/changeset/base/220990
Log:
Break out the PLL setup into an overridable method.
The only method right now is ar5416InitPLL() which handles multiple
chipsets; this can now be overridden by newer chipset HAL code.
Modified:
head/sys/dev/ath/ath_hal/ar5416/ar5416.h
head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416.h
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416.h Sun Apr 24 15:48:07 2011 (r220989)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416.h Sun Apr 24 15:53:57 2011 (r220990)
@@ -103,6 +103,10 @@ struct ath_hal_5416 {
const struct ieee80211_channel *chan,
int16_t *pTxPowerIndexOffset);
+ /* baseband operations */
+ void (*ah_initPLL) (struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
+
u_int ah_globaltxtimeout; /* global tx timeout */
u_int ah_gpioMask;
int ah_hangs; /* h/w hangs state */
@@ -248,6 +252,8 @@ extern void ar5416EepromSetAddac(struct
const struct ieee80211_channel *chan);
extern uint16_t ar5416GetMaxEdgePower(uint16_t freq,
CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
+extern void ar5416InitPLL(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
/* TX power setup related routines in ar5416_reset.c */
extern void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c Sun Apr 24 15:48:07 2011 (r220989)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c Sun Apr 24 15:53:57 2011 (r220990)
@@ -181,6 +181,9 @@ ar5416InitState(struct ath_hal_5416 *ahp
AH5416(ah)->ah_writeIni = ar5416WriteIni;
AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
+ /* Internal baseband ops */
+ AH5416(ah)->ah_initPLL = ar5416InitPLL;
+
/* Internal calibration ops */
AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware;
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Sun Apr 24 15:48:07 2011 (r220989)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Sun Apr 24 15:53:57 2011 (r220990)
@@ -54,7 +54,6 @@ static void ar5416SetDeltaSlope(struct a
static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
-static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
struct ar5416eeprom *pEepData,
const struct ieee80211_channel *chan, int16_t *ratesArray,
@@ -513,7 +512,7 @@ ar5416InitBB(struct ath_hal *ah, const s
/* Turn on PLL on 5416 */
HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n",
__func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz");
- ar5416InitPLL(ah, chan);
+ AH5416(ah)->ah_initPLL(ah, chan);
/* Activate the PHY (includes baseband activate and synthesizer on) */
OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
@@ -655,7 +654,7 @@ ar5416ChipReset(struct ath_hal *ah, cons
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
return AH_FALSE;
- ar5416InitPLL(ah, chan);
+ AH5416(ah)->ah_initPLL(ah, chan);
/*
* Perform warm reset before the mode/PLL/turbo registers
@@ -1221,7 +1220,7 @@ ar5416SetReset(struct ath_hal *ah, int t
OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
}
- ar5416InitPLL(ah, AH_NULL);
+ AH5416(ah)->ah_initPLL(ah, AH_NULL);
return AH_TRUE;
}
@@ -1278,7 +1277,7 @@ ar5416UpdateChainMasks(struct ath_hal *a
#define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE
#endif
-static void
+void
ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint32_t pll;
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