svn commit: r196491 - head/sys/dev/usb/net

[Alfred Perlstein]

Author: alfred
Date: Mon Aug 24 05:00:07 2009
New Revision: 196491
URL: http://svn.freebsd.org/changeset/base/196491

Log:
  We used force all of the GPIO pins low first and then
  enable the ones we want. This has been changed to better
  match the ADMtek's reference design to avoid setting the
  power-down configuration line of the PHY at the same time
  it is reset.
  
  Submitted by:	John Hood via hps

Modified:
  head/sys/dev/usb/net/if_aue.c

Modified: head/sys/dev/usb/net/if_aue.c
==============================================================================
--- head/sys/dev/usb/net/if_aue.c	Mon Aug 24 04:59:09 2009	(r196490)
+++ head/sys/dev/usb/net/if_aue.c	Mon Aug 24 05:00:07 2009	(r196491)
@@ -484,7 +484,7 @@ aue_miibus_writereg(device_t dev, int ph
 	}
 
 	if (i == AUE_TIMEOUT)
-		device_printf(sc->sc_ue.ue_dev, "MII read timed out\n");
+		device_printf(sc->sc_ue.ue_dev, "MII write timed out\n");
 
 	if (!locked)
 		AUE_UNLOCK(sc);
@@ -603,11 +603,14 @@ aue_reset(struct aue_softc *sc)
 	 * to set the GPIO pins high so that the PHY(s) will
 	 * be enabled.
 	 *
-	 * Note: We force all of the GPIO pins low first, *then*
-	 * enable the ones we want.
+	 * NOTE: We used to force all of the GPIO pins low first and then
+	 * enable the ones we want. This has been changed to better
+	 * match the ADMtek's reference design to avoid setting the
+	 * power-down configuration line of the PHY at the same time
+	 * it is reset.
 	 */
-	aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_OUT0|AUE_GPIO_SEL0);
-	aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_OUT0|AUE_GPIO_SEL0|AUE_GPIO_SEL1);
+	aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1);
+	aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0);
 
 	if (sc->sc_flags & AUE_FLAG_LSYS) {
 		/* Grrr. LinkSys has to be different from everyone else. */