svn commit: r366183 - stable/11/sys/dev/usb/controller

[Hans Petter Selasky]

Author: hselasky
Date: Sat Sep 26 08:45:08 2020
New Revision: 366183
URL: https://svnweb.freebsd.org/changeset/base/366183

Log:
  MFC r365918:
  Fix for use of the XHCI driver on Cortex-A72 by adding a missing cache
  flush operation before writing to the XHCI_ERSTBA_LO/HI register(s).
  
  PR:		237666
  Discussed with:	Mark Millard <marklmi at yahoo.com>
  Sponsored by:	Mellanox Technologies // Nvidia

Modified:
  stable/11/sys/dev/usb/controller/xhci.c
Directory Properties:
  stable/11/   (props changed)

Modified: stable/11/sys/dev/usb/controller/xhci.c
==============================================================================
--- stable/11/sys/dev/usb/controller/xhci.c	Sat Sep 26 08:44:16 2020	(r366182)
+++ stable/11/sys/dev/usb/controller/xhci.c	Sat Sep 26 08:45:08 2020	(r366183)
@@ -429,6 +429,19 @@ xhci_start_controller(struct xhci_softc *sc)
 	phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 	phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 
+	/*
+	 * PR 237666:
+	 *
+	 * According to the XHCI specification, the XWRITE4's to
+	 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the
+	 * qwEvrsTablePtr and dwEvrsTableSize values above at that
+	 * time, as the XHCI initializes its event ring support. This
+	 * is before the event ring starts to pay attention to the
+	 * RUN/STOP bit. Thus, make sure the values are observable to
+	 * the XHCI before that point.
+	 */
+	usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
+
 	DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 
 	XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);