svn commit: r360050 - head/sys/mips/include

[John Baldwin]

Author: jhb
Date: Fri Apr 17 18:24:47 2020
New Revision: 360050
URL: https://svnweb.freebsd.org/changeset/base/360050

Log:
  Use the right type for 64-bit coprocessor registers.
  
  The use of "int" here caused the compiler to believe that it needs to
  insert a "sll $n, $n, 0" to sign extend as part of the implicit cast
  to uint64_t.
  
  Submitted by:	Nathaniel Filardo <nwf20 at cl.cam.ac.uk>
  Reviewed by:	brooks, arichardson
  Obtained from:	CheriBSD
  Sponsored by:	DARPA
  Differential Revision:	https://reviews.freebsd.org/D24457

Modified:
  head/sys/mips/include/cpufunc.h

Modified: head/sys/mips/include/cpufunc.h
==============================================================================
--- head/sys/mips/include/cpufunc.h	Fri Apr 17 18:22:37 2020	(r360049)
+++ head/sys/mips/include/cpufunc.h	Fri Apr 17 18:24:47 2020	(r360050)
@@ -125,7 +125,7 @@ breakpoint(void)
 static __inline uint64_t					\
 mips_rd_ ## n (void)						\
 {								\
-	int v0;							\
+	uint64_t v0;						\
 	__asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";"	\
 			  : [v0] "=&r"(v0));			\
 	mips_barrier();						\
@@ -147,7 +147,7 @@ mips_wr_ ## n (uint64_t a0)					\
 static __inline uint64_t					\
 mips_rd_ ## n(void)						\
 {								\
-	int v0;							\
+	uint64_t v0;						\
 	__asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
 			  : [v0] "=&r"(v0));			\
 	mips_barrier();						\
@@ -190,7 +190,7 @@ MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
 static __inline uint32_t					\
 mips_rd_ ## n (void)						\
 {								\
-	int v0;							\
+	uint32_t v0;						\
 	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";"	\
 			  : [v0] "=&r"(v0));			\
 	mips_barrier();						\
@@ -212,7 +212,7 @@ mips_wr_ ## n (uint32_t a0)					\
 static __inline uint32_t					\
 mips_rd_ ## n(void)						\
 {								\
-	int v0;							\
+	uint32_t v0;						\
 	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
 			  : [v0] "=&r"(v0));			\
 	mips_barrier();						\