svn commit: r347351 - in head/sys: conf riscv/conf

[Ruslan Bukin]

Author: br
Date: Wed May  8 16:06:54 2019
New Revision: 347351
URL: https://svnweb.freebsd.org/changeset/base/347351

Log:
  Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build.
  
  Sponsored by:	DARPA, AFRL

Modified:
  head/sys/conf/files.riscv
  head/sys/riscv/conf/GENERIC

Modified: head/sys/conf/files.riscv
==============================================================================
--- head/sys/conf/files.riscv	Wed May  8 16:05:18 2019	(r347350)
+++ head/sys/conf/files.riscv	Wed May  8 16:06:54 2019	(r347351)
@@ -5,10 +5,13 @@ cddl/dev/dtrace/riscv/dtrace_subr.c			optional dtrace 
 cddl/dev/fbt/riscv/fbt_isa.c				optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
 crypto/blowfish/bf_enc.c	optional	crypto | ipsec | ipsec_support
 crypto/des/des_enc.c		optional	crypto | ipsec | ipsec_support | netsmb
+dev/cadence/if_cgem.c		optional	cgem
 dev/ofw/ofw_cpu.c		optional	fdt
 dev/uart/uart_cpu_fdt.c		optional	uart fdt
 dev/uart/uart_dev_lowrisc.c	optional	uart_lowrisc
 dev/xilinx/axi_quad_spi.c	optional	xilinx_spi
+dev/xilinx/axidma.c		optional	axidma xdma
+dev/xilinx/if_xae.c		optional	xae
 kern/kern_clocksource.c		standard
 kern/msi_if.m			standard
 kern/pic_if.m			standard

Modified: head/sys/riscv/conf/GENERIC
==============================================================================
--- head/sys/riscv/conf/GENERIC	Wed May  8 16:05:18 2019	(r347350)
+++ head/sys/riscv/conf/GENERIC	Wed May  8 16:06:54 2019	(r347351)
@@ -102,6 +102,16 @@ device		uart		# Generic UART driver
 device		uart_lowrisc	# lowRISC UART driver
 device		uart_ns8250	# ns8250-type UART driver
 
+
+# Ethernet drivers
+device		miibus		# MII bus support
+device		cgem		# Cadence Gigabit Ethernet MAC
+device		xae		# Xilinx AXI Ethernet MAC
+
+# DMA support
+device		xdma		# DMA interface
+device		axidma		# Xilinx AXI DMA Controller
+
 # Uncomment for memory disk
 # options 	MD_ROOT
 # options 	MD_ROOT_SIZE=32768	# 32MB ram disk