svn commit: r346791 - head/sys/powerpc/include

[Justin Hibbits]

Author: jhibbits
Date: Sat Apr 27 19:32:33 2019
New Revision: 346791
URL: https://svnweb.freebsd.org/changeset/base/346791

Log:
  powerpc: Add SPR definitions for additional POWER8/POWER9 facilities
  
  This only adds the new SPR definitions and the associated FSCR bits.  The
  facilities themselves will be added in separate commits.

Modified:
  head/sys/powerpc/include/spr.h

Modified: head/sys/powerpc/include/spr.h
==============================================================================
--- head/sys/powerpc/include/spr.h	Sat Apr 27 16:28:34 2019	(r346790)
+++ head/sys/powerpc/include/spr.h	Sat Apr 27 19:32:33 2019	(r346791)
@@ -136,7 +136,13 @@
 #define	  FSCR_IC_STOP		  0x0900000000000000ULL	/* Access to the 'stop' instruction in privileged non-hypervisor state */
 #define	  FSCR_IC_MSG		  0x0A00000000000000ULL	/* Access to 'msgsndp' or 'msgclrp' instructions */
 #define	  FSCR_IC_SCV		  0x0C00000000000000ULL	/* Execution of a 'scv' instruction */
+#define	  FSCR_SCV		  0x0000000000001000ULL /* scv instruction available */
+#define	  FSCR_LM		  0x0000000000000800ULL /* Load monitored facilities available */
+#define	  FSCR_MSGP		  0x0000000000000400ULL /* msgsndp and SPRs available */
+#define	  FSCR_TAR		  0x0000000000000100ULL /* TAR register available */
+#define	  FSCR_EBB		  0x0000000000000080ULL /* Event-based branch available */
 #define	  FSCR_DSCR		  0x0000000000000004ULL	/* DSCR available in PR state */
+#define	SPR_DPDES		0x0b0	/* .6. Directed Privileged Doorbell Exception State Register */
 #define	SPR_USPRG0		0x100	/* 4.. User SPR General 0 */
 #define	SPR_VRSAVE		0x100	/* .6. AltiVec VRSAVE */
 #define	SPR_SPRG0		0x110	/* 468 SPR General 0 */
@@ -248,6 +254,7 @@
 #define	SPR_HMER		0x150	/* Hypervisor Maintenance Exception Register */
 #define	SPR_HMEER		0x151	/* Hypervisor Maintenance Exception Enable Register */
 
+#define	SPR_TIR			0x1be	/* .6. Thread Identification Register */
 #define	SPR_PTCR		0x1d0	/* Partition Table Control Register */
 #define	SPR_SPEFSCR		0x200	/* ..8 Signal Processing Engine FSCR. */
 #define	  SPEFSCR_SOVH		  0x80000000
@@ -408,6 +415,16 @@
 #define	SPR_MD_TWC		0x31d	/* ..8 DMMU tablewalk control */
 #define	SPR_MD_RPN		0x31e	/* ..8 DMMU real (phys) page number */
 #define	SPR_MD_TW		0x31f	/* ..8 MMU tablewalk scratch */
+#define	SPR_BESCRS		0x320	/* .6. Branch Event Status and Control Set Register */
+#define	SPR_BESCRSU		0x321	/* .6. Branch Event Status and Control Set Register (upper 32-bit) */
+#define	SPR_BESCRR		0x322	/* .6. Branch Event Status and Control Reset Register */
+#define	SPR_BESCRRU		0x323	/* .6. Branch Event Status and Control Register (upper 32-bit) */
+#define	SPR_EBBHR		0x324	/* .6. Event-based Branch Handler Register */
+#define	SPR_EBBRR		0x325	/* .6. Event-based Branch Return Register */
+#define	SPR_BESCR		0x326	/* .6. Branch Event Status and Control Register */
+#define	SPR_LMRR		0x32d	/* .6. Load Monitored Region Register */
+#define	SPR_LMSER		0x32e	/* .6. Load Monitored Section Enable Register */
+#define	SPR_TAR			0x32f	/* .6. Branch Target Address Register */
 #define	SPR_MI_CAM		0x330	/* ..8 IMMU CAM entry read */
 #define	SPR_MI_RAM0		0x331	/* ..8 IMMU RAM entry read reg 0 */
 #define	SPR_MI_RAM1		0x332	/* ..8 IMMU RAM entry read reg 1 */