svn commit: r340488 - in head/sys/x86: include x86 xen

[John Baldwin]

Author: jhb
Date: Fri Nov 16 23:39:39 2018
New Revision: 340488
URL: https://svnweb.freebsd.org/changeset/base/340488

Log:
  Axe MINIMUM_MSI_INT.
  
  Just allow MSI interrupts to always start at the end of the I/O APIC
  pins.  Since existing machines already have more than 255 I/O APIC
  pins, IRQ 255 is no longer reliably invalid, so just remove the
  minimum starting value for MSI.
  
  Reviewed by:	kib, markj
  Differential Revision:	https://reviews.freebsd.org/D17991

Modified:
  head/sys/x86/include/intr_machdep.h
  head/sys/x86/x86/msi.c
  head/sys/x86/xen/pvcpu_enum.c
  head/sys/x86/xen/xen_msi.c

Modified: head/sys/x86/include/intr_machdep.h
==============================================================================
--- head/sys/x86/include/intr_machdep.h	Fri Nov 16 21:27:11 2018	(r340487)
+++ head/sys/x86/include/intr_machdep.h	Fri Nov 16 23:39:39 2018	(r340488)
@@ -51,15 +51,11 @@
  * IRQ values returned by ACPI methods such as _CRS can be used
  * directly by the ACPI bus driver.
  *
- * MSI interrupts allocate a block of interrupts starting at either
- * the end of the I/O APIC range or 256, whichever is higher.  When
- * running under the Xen Hypervisor, an additional range of IRQ values
- * are available for binding to event channel events.  We use 256 as
- * the minimum IRQ value for MSI interrupts to attempt to leave 255
- * unused since 255 is used in PCI to indicate an invalid INTx IRQ.
+ * MSI interrupts allocate a block of interrupts starting at the end
+ * of the I/O APIC range.  When running under the Xen Hypervisor, an
+ * additional range of IRQ values are available for binding to event
+ * channel events.
  */
-#define	MINIMUM_MSI_INT	256
-
 extern u_int first_msi_irq;
 extern u_int num_io_irqs;
 extern u_int num_msi_irqs;

Modified: head/sys/x86/x86/msi.c
==============================================================================
--- head/sys/x86/x86/msi.c	Fri Nov 16 21:27:11 2018	(r340487)
+++ head/sys/x86/x86/msi.c	Fri Nov 16 23:39:39 2018	(r340488)
@@ -153,6 +153,8 @@ struct pic msi_pic = {
 };
 
 u_int first_msi_irq;
+SYSCTL_UINT(_machdep, OID_AUTO, first_msi_irq, CTLFLAG_RD, &first_msi_irq, 0,
+    "Number of first IRQ reserved for MSI and MSI-X interrupts");
 
 u_int num_msi_irqs = 512;
 SYSCTL_UINT(_machdep, OID_AUTO, num_msi_irqs, CTLFLAG_RDTUN, &num_msi_irqs, 0,
@@ -339,7 +341,7 @@ msi_init(void)
 	if (num_msi_irqs == 0)
 		return;
 
-	first_msi_irq = max(MINIMUM_MSI_INT, num_io_irqs);
+	first_msi_irq = num_io_irqs;
 	if (num_msi_irqs > UINT_MAX - first_msi_irq)
 		panic("num_msi_irq too high");
 	num_io_irqs = first_msi_irq + num_msi_irqs;

Modified: head/sys/x86/xen/pvcpu_enum.c
==============================================================================
--- head/sys/x86/xen/pvcpu_enum.c	Fri Nov 16 21:27:11 2018	(r340487)
+++ head/sys/x86/xen/pvcpu_enum.c	Fri Nov 16 23:39:39 2018	(r340488)
@@ -199,7 +199,7 @@ xenpv_setup_io(void)
 		 * this is legacy code so just keep using the previous
 		 * behaviour and assume a maximum of 256 interrupts.
 		 */
-		num_io_irqs = max(MINIMUM_MSI_INT - 1, num_io_irqs);
+		num_io_irqs = max(255, num_io_irqs);
 
 		acpi_SetDefaultIntrModel(ACPI_INTR_APIC);
 	}

Modified: head/sys/x86/xen/xen_msi.c
==============================================================================
--- head/sys/x86/xen/xen_msi.c	Fri Nov 16 21:27:11 2018	(r340487)
+++ head/sys/x86/xen/xen_msi.c	Fri Nov 16 23:39:39 2018	(r340488)
@@ -57,7 +57,7 @@ xen_msi_init(void)
 {
 
 	MPASS(num_io_irqs > 0);
-	first_msi_irq = min(MINIMUM_MSI_INT, num_io_irqs);
+	first_msi_irq = num_io_irqs;
 	if (num_msi_irqs > UINT_MAX - first_msi_irq)
 		panic("num_msi_irq too high");
 	num_io_irqs = first_msi_irq + num_msi_irqs;