svn commit: r322053 - head/sys/arm64/arm64

[Andrew Turner]

Author: andrew
Date: Fri Aug  4 13:08:45 2017
New Revision: 322053
URL: https://svnweb.freebsd.org/changeset/base/322053

Log:
  Start to teach the GICv3 driver about NUMA. On ThunderX we may have
  multiple ITS devices, however we only want a single ITS device to be
  configured on each CPU. To fix this only enable ITS when the node matches
  the CPUs node.
  
  Sponsored by:	DARPA, AFRL

Modified:
  head/sys/arm64/arm64/gic_v3.c
  head/sys/arm64/arm64/gic_v3_fdt.c
  head/sys/arm64/arm64/gic_v3_var.h
  head/sys/arm64/arm64/gicv3_its.c

Modified: head/sys/arm64/arm64/gic_v3.c
==============================================================================
--- head/sys/arm64/arm64/gic_v3.c	Fri Aug  4 12:57:24 2017	(r322052)
+++ head/sys/arm64/arm64/gic_v3.c	Fri Aug  4 13:08:45 2017	(r322053)
@@ -69,6 +69,7 @@ __FBSDID("$FreeBSD$");
 #include "gic_v3_reg.h"
 #include "gic_v3_var.h"
 
+static bus_get_domain_t gic_v3_get_domain;
 static bus_read_ivar_t gic_v3_read_ivar;
 
 static pic_disable_intr_t gic_v3_disable_intr;
@@ -97,6 +98,7 @@ static device_method_t gic_v3_methods[] = {
 	DEVMETHOD(device_detach,	gic_v3_detach),
 
 	/* Bus interface */
+	DEVMETHOD(bus_get_domain,	gic_v3_get_domain),
 	DEVMETHOD(bus_read_ivar,	gic_v3_read_ivar),
 
 	/* Interrupt controller interface */
@@ -347,6 +349,19 @@ gic_v3_detach(device_t dev)
 	free(sc->gic_res, M_GIC_V3);
 	free(sc->gic_redists.regions, M_GIC_V3);
 
+	return (0);
+}
+
+static int
+gic_v3_get_domain(device_t dev, device_t child, int *domain)
+{
+	struct gic_v3_devinfo *di;
+
+	di = device_get_ivars(child);
+	if (di->gic_domain < 0)
+		return (ENOENT);
+
+	*domain = di->gic_domain;
 	return (0);
 }
 

Modified: head/sys/arm64/arm64/gic_v3_fdt.c
==============================================================================
--- head/sys/arm64/arm64/gic_v3_fdt.c	Fri Aug  4 12:57:24 2017	(r322052)
+++ head/sys/arm64/arm64/gic_v3_fdt.c	Fri Aug  4 13:08:45 2017	(r322053)
@@ -186,6 +186,7 @@ error:
 
 /* OFW bus interface */
 struct gic_v3_ofw_devinfo {
+	struct gic_v3_devinfo	di_gic_dinfo;
 	struct ofw_bus_devinfo	di_dinfo;
 	struct resource_list	di_rl;
 };
@@ -281,6 +282,14 @@ gic_v3_ofw_bus_attach(device_t dev)
 		for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
 			/* Allocate and populate devinfo. */
 			di = malloc(sizeof(*di), M_GIC_V3, M_WAITOK | M_ZERO);
+
+			/* Read the numa node, or -1 if there is none */
+			if (OF_getencprop(node, "numa-node-id",
+			    &di->di_gic_dinfo.gic_domain,
+			    sizeof(di->di_gic_dinfo.gic_domain)) <= 0) {
+				di->di_gic_dinfo.gic_domain = -1;
+			}
+
 			if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node)) {
 				if (bootverbose) {
 					device_printf(dev,

Modified: head/sys/arm64/arm64/gic_v3_var.h
==============================================================================
--- head/sys/arm64/arm64/gic_v3_var.h	Fri Aug  4 12:57:24 2017	(r322052)
+++ head/sys/arm64/arm64/gic_v3_var.h	Fri Aug  4 13:08:45 2017	(r322053)
@@ -82,6 +82,11 @@ struct gic_v3_softc {
 	struct gic_v3_irqsrc	*gic_irqs;
 };
 
+
+struct gic_v3_devinfo {
+	int gic_domain;
+};
+
 #define GIC_INTR_ISRC(sc, irq)	(&sc->gic_irqs[irq].gi_isrc)
 
 MALLOC_DECLARE(M_GIC_V3);

Modified: head/sys/arm64/arm64/gicv3_its.c
==============================================================================
--- head/sys/arm64/arm64/gicv3_its.c	Fri Aug  4 12:57:24 2017	(r322052)
+++ head/sys/arm64/arm64/gicv3_its.c	Fri Aug  4 13:08:45 2017	(r322053)
@@ -576,6 +576,12 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
 	uint64_t xbaser, tmp;
 	uint32_t ctlr;
 	u_int cpuid;
+	int domain;
+
+	if (bus_get_domain(dev, &domain) == 0) {
+		if (PCPU_GET(domain) != domain)
+			return (0);
+	}
 
 	gicv3 = device_get_parent(dev);
 	cpuid = PCPU_GET(cpuid);