svn commit: r305475 - in vendor-sys/alpine-hal: 2.7a 2.7a/eth dist dist/eth
Wojciech Macek
wma at FreeBSD.org
Tue Sep 6 14:26:43 UTC 2016
Author: wma
Date: Tue Sep 6 14:26:41 2016
New Revision: 305475
URL: https://svnweb.freebsd.org/changeset/base/305475
Log:
Update Annapurna Alpine HAL to a newer version.
HAL version: 2.7a
Added:
vendor-sys/alpine-hal/2.7a/
vendor-sys/alpine-hal/2.7a/al_hal_common.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_iofic.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_iofic.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_iofic_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_nb_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pbs_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pcie.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pcie.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pcie_axi_reg.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pcie_interrupts.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pcie_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_pcie_w_reg.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_plat_services.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_plat_types.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_reg_utils.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_25g.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_25g.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_25g_internal_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_25g_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_hssp.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_hssp_internal_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_hssp_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_interface.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_internal_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_serdes_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_types.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_config.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_config.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_debug.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_debug.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_iofic.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_iofic.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_iofic_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_main.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_regs_gen.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_regs_m2s.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_udma_regs_s2m.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_hal_unit_adapter_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_serdes.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/al_serdes.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/
vendor-sys/alpine-hal/2.7a/eth/al_hal_an_lt_wrapper_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth_alu.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth_ec_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth_kr.c (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth_kr.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth_mac_regs.h (contents, props changed)
vendor-sys/alpine-hal/2.7a/eth/al_hal_eth_main.c (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_25g.c (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_25g.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_25g_internal_regs.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_25g_regs.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_hssp.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_hssp_internal_regs.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_hssp_regs.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_hal_serdes_interface.h (contents, props changed)
vendor-sys/alpine-hal/dist/al_serdes.c (contents, props changed)
vendor-sys/alpine-hal/dist/al_serdes.h (contents, props changed)
Modified:
vendor-sys/alpine-hal/dist/al_hal_iofic.c
vendor-sys/alpine-hal/dist/al_hal_iofic.h
vendor-sys/alpine-hal/dist/al_hal_iofic_regs.h
vendor-sys/alpine-hal/dist/al_hal_nb_regs.h
vendor-sys/alpine-hal/dist/al_hal_pbs_regs.h
vendor-sys/alpine-hal/dist/al_hal_pcie.c
vendor-sys/alpine-hal/dist/al_hal_pcie.h
vendor-sys/alpine-hal/dist/al_hal_pcie_axi_reg.h
vendor-sys/alpine-hal/dist/al_hal_pcie_interrupts.h
vendor-sys/alpine-hal/dist/al_hal_pcie_regs.h
vendor-sys/alpine-hal/dist/al_hal_pcie_w_reg.h
vendor-sys/alpine-hal/dist/al_hal_plat_services.h
vendor-sys/alpine-hal/dist/al_hal_plat_types.h
vendor-sys/alpine-hal/dist/al_hal_reg_utils.h
vendor-sys/alpine-hal/dist/al_hal_serdes.c
vendor-sys/alpine-hal/dist/al_hal_serdes.h
vendor-sys/alpine-hal/dist/al_hal_udma.h
vendor-sys/alpine-hal/dist/al_hal_udma_config.c
vendor-sys/alpine-hal/dist/al_hal_udma_config.h
vendor-sys/alpine-hal/dist/al_hal_udma_debug.c
vendor-sys/alpine-hal/dist/al_hal_udma_iofic.h
vendor-sys/alpine-hal/dist/al_hal_udma_main.c
vendor-sys/alpine-hal/dist/al_hal_udma_regs_gen.h
vendor-sys/alpine-hal/dist/al_hal_unit_adapter_regs.h
vendor-sys/alpine-hal/dist/eth/al_hal_eth.h
vendor-sys/alpine-hal/dist/eth/al_hal_eth_mac_regs.h
vendor-sys/alpine-hal/dist/eth/al_hal_eth_main.c
Added: vendor-sys/alpine-hal/2.7a/al_hal_common.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor-sys/alpine-hal/2.7a/al_hal_common.h Tue Sep 6 14:26:41 2016 (r305475)
@@ -0,0 +1,70 @@
+/*-
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_common HAL Common Layer
+ * Includes all common header files used by HAL
+ * @{
+ * @file al_hal_common.h
+ *
+ */
+
+#ifndef __AL_HAL_COMMON_H__
+#define __AL_HAL_COMMON_H__
+
+#include "al_hal_plat_types.h"
+#include "al_hal_plat_services.h"
+
+#include "al_hal_types.h"
+#include "al_hal_reg_utils.h"
+
+/* Get the maximal value out of two typed values */
+#define al_max_t(type, x, y) ({ \
+ type __max1 = (x); \
+ type __max2 = (y); \
+ __max1 > __max2 ? __max1 : __max2; })
+
+/* Get the minimal value out of two typed values */
+#define al_min_t(type, x, y) ({ \
+ type __min1 = (x); \
+ type __min2 = (y); \
+ __min1 < __min2 ? __min1 : __min2; })
+
+/* Get the number of elements in an array */
+#define AL_ARR_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+/** @} end of Common group */
+#endif /* __AL_HAL_COMMON_H__ */
Added: vendor-sys/alpine-hal/2.7a/al_hal_iofic.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor-sys/alpine-hal/2.7a/al_hal_iofic.c Tue Sep 6 14:26:41 2016 (r305475)
@@ -0,0 +1,291 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @{
+ * @file al_hal_iofic.c
+ *
+ * @brief interrupt controller hal
+ *
+ */
+
+#include "al_hal_iofic.h"
+#include "al_hal_iofic_regs.h"
+
+/*
+ * configure the interrupt registers, interrupts will are kept masked
+ */
+int al_iofic_config(void __iomem *regs_base, int group, uint32_t flags)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ al_reg_write32(®s->ctrl[group].int_control_grp, flags);
+
+ return 0;
+}
+
+/*
+ * configure the moderation timer resolution for a given group
+ */
+int al_iofic_moder_res_config(void __iomem *regs_base, int group,
+ uint8_t resolution)
+
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+ uint32_t reg;
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ reg = al_reg_read32(®s->ctrl[group].int_control_grp);
+ AL_REG_FIELD_SET(reg,
+ INT_CONTROL_GRP_MOD_RES_MASK,
+ INT_CONTROL_GRP_MOD_RES_SHIFT,
+ resolution);
+ al_reg_write32(®s->ctrl[group].int_control_grp, reg);
+
+ return 0;
+}
+
+/*
+ * configure the moderation timer interval for a given legacy interrupt group
+ */
+int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
+ uint8_t interval)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+ uint32_t reg;
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ reg = al_reg_read32(®s->ctrl[group].int_control_grp);
+ AL_REG_FIELD_SET(reg,
+ INT_CONTROL_GRP_MOD_INTV_MASK,
+ INT_CONTROL_GRP_MOD_INTV_SHIFT,
+ interval);
+ al_reg_write32(®s->ctrl[group].int_control_grp, reg);
+
+ return 0;
+}
+
+
+/*
+ * configure the moderation timer interval for a given msix vector.
+ */
+int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
+ uint8_t vector, uint8_t interval)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+ uint32_t reg;
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ reg = al_reg_read32(®s->grp_int_mod[group][vector].grp_int_mod_reg);
+ AL_REG_FIELD_SET(reg,
+ INT_MOD_INTV_MASK,
+ INT_MOD_INTV_SHIFT,
+ interval);
+ al_reg_write32(®s->grp_int_mod[group][vector].grp_int_mod_reg, reg);
+
+ return 0;
+}
+
+/*
+ * configure the target-id attributes for a given msix vector.
+ */
+int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group,
+ uint8_t vector, uint32_t tgtid, uint8_t tgtid_en)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+ uint32_t reg = 0;
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ AL_REG_FIELD_SET(reg,
+ INT_MSIX_TGTID_MASK,
+ INT_MSIX_TGTID_SHIFT,
+ tgtid);
+ AL_REG_BIT_VAL_SET(reg,
+ INT_MSIX_TGTID_EN_SHIFT,
+ tgtid_en);
+
+ al_reg_write32(®s->grp_int_mod[group][vector].grp_int_tgtid_reg, reg);
+
+ return 0;
+}
+
+/*
+ * return the offset of the unmask register for a given group
+ */
+uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ return ®s->ctrl[group].int_mask_clear_grp;
+}
+
+
+/*
+ * unmask specific interrupts for a given group
+ */
+void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ /*
+ * use the mask clear register, no need to read the mask register
+ * itself. write 0 to unmask, 1 has no effect
+ */
+ al_reg_write32_relaxed(®s->ctrl[group].int_mask_clear_grp, ~mask);
+}
+
+/*
+ * mask specific interrupts for a given group
+ */
+void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+ uint32_t reg;
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ reg = al_reg_read32(®s->ctrl[group].int_mask_grp);
+
+ al_reg_write32(®s->ctrl[group].int_mask_grp, reg | mask);
+}
+
+/*
+ * read the mask for a given group
+ */
+uint32_t al_iofic_read_mask(void __iomem *regs_base, int group)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ return al_reg_read32(®s->ctrl[group].int_mask_grp);
+}
+
+/*
+ * read interrupt cause register for a given group
+ */
+uint32_t al_iofic_read_cause(void __iomem *regs_base, int group)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ return al_reg_read32(®s->ctrl[group].int_cause_grp);
+}
+
+/*
+ * clear bits in the interrupt cause register for a given group
+ */
+void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ /* inverse mask, writing 1 has no effect */
+ al_reg_write32(®s->ctrl[group].int_cause_grp, ~mask);
+}
+
+/*
+ * Set the cause register for a given group
+ */
+void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ al_reg_write32(®s->ctrl[group].int_cause_set_grp, mask);
+}
+
+
+/*
+ * unmask specific interrupts from aborting the udma a given group
+ */
+void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ al_reg_write32(®s->ctrl[group].int_abort_msk_grp, mask);
+
+}
+
+/*
+ * trigger all interrupts that are waiting for moderation timers to expire
+ */
+void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group)
+{
+ struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+ uint32_t reg = 0;
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ al_assert(regs_base);
+ al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+ reg = al_reg_read32(®s->ctrl[group].int_control_grp);
+ reg |= INT_CONTROL_GRP_MOD_RST;
+
+ al_reg_write32(®s->ctrl[group].int_control_grp, reg);
+}
+
+/** @} end of interrupt controller group */
Added: vendor-sys/alpine-hal/2.7a/al_hal_iofic.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor-sys/alpine-hal/2.7a/al_hal_iofic.h Tue Sep 6 14:26:41 2016 (r305475)
@@ -0,0 +1,222 @@
+/*-
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_interrupts Common I/O Fabric Interrupt Controller
+ * This HAL provides the API for programming the Common I/O Fabric Interrupt
+ * Controller (IOFIC) found in most of the units attached to the I/O Fabric of
+ * Alpine platform
+ * @{
+ * @file al_hal_iofic.h
+ *
+ * @brief Header file for the interrupt controller that's embedded in various units
+ *
+ */
+
+#ifndef __AL_HAL_IOFIC_H__
+#define __AL_HAL_IOFIC_H__
+
+#include <al_hal_common.h>
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#define AL_IOFIC_MAX_GROUPS 4
+
+/*
+ * Configurations
+ */
+
+/**
+ * Configure the interrupt controller registers, actual interrupts are still
+ * masked at this stage.
+ *
+ * @param regs_base regs pointer to interrupt controller registers
+ * @param group the interrupt group.
+ * @param flags flags of Interrupt Control Register
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_config(void __iomem *regs_base, int group,
+ uint32_t flags);
+
+/**
+ * configure the moderation timer resolution for a given group
+ * Applies for both msix and legacy mode.
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param resolution resolution of the timer interval, the resolution determines the rate
+ * of decrementing the interval timer, setting value N means that the interval
+ * timer will be decremented each (N+1) * (0.68) micro seconds.
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_moder_res_config(void __iomem *regs_base, int group,
+ uint8_t resolution);
+
+/**
+ * configure the moderation timer interval for a given legacy interrupt group
+ *
+ * @param regs_base regs pointer to unit registers
+ * @param group the interrupt group
+ * @param interval between interrupts in resolution units. 0 disable
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
+ uint8_t interval);
+
+/**
+ * configure the moderation timer interval for a given msix vector
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param vector vector index
+ * @param interval interval between interrupts, 0 disable
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
+ uint8_t vector, uint8_t interval);
+
+/**
+* configure the tgtid attributes for a given msix vector.
+*
+* @param group the interrupt group
+* @param vector index
+* @param tgtid the target-id value
+* @param tgtid_en take target-id from the intc
+*
+* @return 0 on success. -EINVAL otherwise.
+*/
+int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group,
+ uint8_t vector, uint32_t tgtid, uint8_t tgtid_en);
+
+/**
+ * return the offset of the unmask register for a given group.
+ * this function can be used when the upper layer wants to directly
+ * access the unmask regiter and bypass the al_iofic_unmask() API.
+ *
+ * @param regs_base regs pointer to unit registers
+ * @param group the interrupt group
+ * @return the offset of the unmask register.
+ */
+uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group);
+
+/**
+ * unmask specific interrupts for a given group
+ * this functions guarantees atomic operations, it is performance optimized as
+ * it will not require read-modify-write. The unmask done using the interrupt
+ * mask clear register, so it's safe to call it while the mask is changed by
+ * the HW (auto mask) or another core.
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of interrupts to unmask, set bits will be unmasked.
+ */
+void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * mask specific interrupts for a given group
+ * this functions modifies interrupt mask register, the callee must make sure
+ * the mask is not changed by another cpu.
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of interrupts to mask, set bits will be masked.
+ */
+void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * read the mask register for a given group
+ * this functions return the interrupt mask register
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ */
+uint32_t al_iofic_read_mask(void __iomem *regs_base, int group);
+
+/**
+ * read interrupt cause register for a given group
+ * this will clear the set bits if the Clear on Read mode enabled.
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ */
+uint32_t al_iofic_read_cause(void __iomem *regs_base, int group);
+
+/**
+ * clear bits in the interrupt cause register for a given group
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of bits to be cleared, set bits will be cleared.
+ */
+void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * set the cause register for a given group
+ * this function set the cause register. It will generate an interrupt (if
+ * the the interrupt isn't masked )
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of bits to be set.
+ */
+void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * unmask specific interrupts from aborting the udma a given group
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of interrupts to mask
+ */
+void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * trigger all interrupts that are waiting for moderation timers to expire
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ */
+void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group);
+
+#endif
+/** @} end of interrupt controller group */
Added: vendor-sys/alpine-hal/2.7a/al_hal_iofic_regs.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor-sys/alpine-hal/2.7a/al_hal_iofic_regs.h Tue Sep 6 14:26:41 2016 (r305475)
@@ -0,0 +1,127 @@
+/*_
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __AL_HAL_IOFIC_REG_H
+#define __AL_HAL_IOFIC_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+struct al_iofic_grp_ctrl {
+ uint32_t int_cause_grp; /* Interrupt Cause RegisterSet by hardware */
+ uint32_t rsrvd1;
+ uint32_t int_cause_set_grp; /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */
+ uint32_t rsrvd2;
+ uint32_t int_mask_grp; /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */
+ uint32_t rsrvd3;
+ uint32_t int_mask_clear_grp; /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */
+ uint32_t rsrvd4;
+ uint32_t int_status_grp; /* Interrupt status RegisterThis register latch the st ... */
+ uint32_t rsrvd5;
+ uint32_t int_control_grp; /* Interrupt Control Register */
+ uint32_t rsrvd6;
+ uint32_t int_abort_msk_grp; /* Interrupt Mask RegisterEach bit in this register ma ... */
+ uint32_t rsrvd7;
+ uint32_t int_log_msk_grp; /* Interrupt Log RegisterEach bit in this register mas ... */
+ uint32_t rsrvd8;
+};
+
+struct al_iofic_grp_mod {
+ uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */
+ uint32_t grp_int_tgtid_reg;
+};
+
+struct al_iofic_regs {
+ struct al_iofic_grp_ctrl ctrl[0];
+ uint32_t rsrvd1[0x400 >> 2];
+ struct al_iofic_grp_mod grp_int_mod[0][32];
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** int_control_grp register ****/
+/* When Clear_on_Read =1, All bits of Cause register ... */
+#define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0)
+/* (must be set only when MSIX is enabled)When Auto-Ma ... */
+#define INT_CONTROL_GRP_AUTO_MASK (1 << 1)
+/* Auto_Clear (RW)When Auto-Clear =1, the bits in the ... */
+#define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2)
+/* When Set_on_Posedge =1, the bits in the interrupt c ... */
+#define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3)
+/* When Moderation_Reset =1, all Moderation timers ass ... */
+#define INT_CONTROL_GRP_MOD_RST (1 << 4)
+/* When mask_msi_x =1, No MSI-X from this group is sen ... */
+#define INT_CONTROL_GRP_MASK_MSI_X (1 << 5)
+/* MSI-X AWID value, same ID for all cause bits */
+#define INT_CONTROL_GRP_AWID_MASK 0x00000F00
+#define INT_CONTROL_GRP_AWID_SHIFT 8
+/* This value determines the interval between interrup ... */
+#define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000
+#define INT_CONTROL_GRP_MOD_INTV_SHIFT 16
+/* This value determines the Moderation_Timer_Clock sp ... */
+#define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000
+#define INT_CONTROL_GRP_MOD_RES_SHIFT 24
+
+/**** grp_int_mod_reg register ****/
+/* Interrupt Moderation Interval registerDedicated reg ... */
+#define INT_MOD_INTV_MASK 0x000000FF
+#define INT_MOD_INTV_SHIFT 0
+
+/**** grp_int_tgtid_reg register ****/
+/* Interrupt tgtid value registerDedicated reg ... */
+#define INT_MSIX_TGTID_MASK 0x0000FFFF
+#define INT_MSIX_TGTID_SHIFT 0
+/* Interrupt tgtid_en value registerDedicated reg ... */
+#define INT_MSIX_TGTID_EN_SHIFT 31
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_IOFIC_REG_H */
+
+
+
+
Added: vendor-sys/alpine-hal/2.7a/al_hal_nb_regs.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor-sys/alpine-hal/2.7a/al_hal_nb_regs.h Tue Sep 6 14:26:41 2016 (r305475)
@@ -0,0 +1,1826 @@
+/*-
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @{
+ * @file al_hal_nb_regs.h
+ *
+ * @brief North Bridge service registers
+ *
+ */
+
+#ifndef __AL_HAL_NB_REGS_H__
+#define __AL_HAL_NB_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct al_nb_global {
+ /* [0x0] */
+ uint32_t cpus_config;
+ /* [0x4] */
+ uint32_t cpus_secure;
+ /* [0x8] Force init reset. */
+ uint32_t cpus_init_control;
+ /* [0xc] Force init reset per DECEI mode. */
+ uint32_t cpus_init_status;
+ /* [0x10] */
+ uint32_t nb_int_cause;
+ /* [0x14] */
+ uint32_t sev_int_cause;
+ /* [0x18] */
+ uint32_t pmus_int_cause;
+ /* [0x1c] */
+ uint32_t sev_mask;
+ /* [0x20] */
+ uint32_t cpus_hold_reset;
+ /* [0x24] */
+ uint32_t cpus_software_reset;
+ /* [0x28] */
+ uint32_t wd_timer0_reset;
+ /* [0x2c] */
+ uint32_t wd_timer1_reset;
+ /* [0x30] */
+ uint32_t wd_timer2_reset;
+ /* [0x34] */
+ uint32_t wd_timer3_reset;
+ /* [0x38] */
+ uint32_t ddrc_hold_reset;
+ /* [0x3c] */
+ uint32_t fabric_software_reset;
+ /* [0x40] */
+ uint32_t cpus_power_ctrl;
+ uint32_t rsrvd_0[7];
+ /* [0x60] */
+ uint32_t acf_base_high;
+ /* [0x64] */
+ uint32_t acf_base_low;
+ /* [0x68] */
+ uint32_t acf_control_override;
+ /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
+ uint32_t lgic_base_high;
+ /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
+ uint32_t lgic_base_low;
+ /* [0x74] Read-only that reflects the device's IOGIC base high address. */
+ uint32_t iogic_base_high;
+ /* [0x78] Read-only that reflects IOGIC base low address */
+ uint32_t iogic_base_low;
+ /* [0x7c] */
+ uint32_t io_wr_split_control;
+ /* [0x80] */
+ uint32_t io_rd_rob_control;
+ /* [0x84] */
+ uint32_t sb_pos_error_log_1;
+ /* [0x88] */
+ uint32_t sb_pos_error_log_0;
+ /* [0x8c] */
+ uint32_t c2swb_config;
+ /* [0x90] */
+ uint32_t msix_error_log;
+ /* [0x94] */
+ uint32_t error_cause;
+ /* [0x98] */
+ uint32_t error_mask;
+ uint32_t rsrvd_1;
+ /* [0xa0] */
+ uint32_t qos_peak_control;
+ /* [0xa4] */
+ uint32_t qos_set_control;
+ /* [0xa8] */
+ uint32_t ddr_qos;
+ uint32_t rsrvd_2[9];
+ /* [0xd0] */
+ uint32_t acf_misc;
+ /* [0xd4] */
+ uint32_t config_bus_control;
+ uint32_t rsrvd_3[2];
+ /* [0xe0] */
+ uint32_t pos_id_match;
+ uint32_t rsrvd_4[3];
+ /* [0xf0] */
+ uint32_t sb_sel_override_awuser;
+ /* [0xf4] */
+ uint32_t sb_override_awuser;
+ /* [0xf8] */
+ uint32_t sb_sel_override_aruser;
+ /* [0xfc] */
+ uint32_t sb_override_aruser;
+ /* [0x100] */
+ uint32_t cpu_max_pd_timer;
+ /* [0x104] */
+ uint32_t cpu_max_pu_timer;
+ uint32_t rsrvd_5[2];
+ /* [0x110] */
+ uint32_t auto_ddr_self_refresh_counter;
+ uint32_t rsrvd_6[3];
+ /* [0x120] */
+ uint32_t coresight_pd;
+ /* [0x124] */
+ uint32_t coresight_internal_0;
+ /* [0x128] */
+ uint32_t coresight_dbgromaddr;
+ /* [0x12c] */
+ uint32_t coresight_dbgselfaddr;
+ /* [0x130] */
+ uint32_t coresght_targetid;
+ /* [0x134] */
+ uint32_t coresght_targetid0;
+ uint32_t rsrvd_7[10];
+ /* [0x160] */
+ uint32_t sb_force_same_id_cfg_0;
+ /* [0x164] */
+ uint32_t sb_mstr_force_same_id_sel_0;
+ /* [0x168] */
+ uint32_t sb_force_same_id_cfg_1;
+ /* [0x16c] */
+ uint32_t sb_mstr_force_same_id_sel_1;
+ uint32_t rsrvd[932];
+};
+struct al_nb_system_counter {
+ /* [0x0] */
+ uint32_t cnt_control;
+ /* [0x4] */
+ uint32_t cnt_base_freq;
+ /* [0x8] */
+ uint32_t cnt_low;
+ /* [0xc] */
+ uint32_t cnt_high;
+ /* [0x10] */
+ uint32_t cnt_init_low;
+ /* [0x14] */
+ uint32_t cnt_init_high;
+ uint32_t rsrvd[58];
+};
+struct al_nb_rams_control_misc {
+ /* [0x0] */
+ uint32_t ca15_rf_misc;
+ uint32_t rsrvd_0;
+ /* [0x8] */
+ uint32_t nb_rf_misc;
+ uint32_t rsrvd[61];
+};
+struct al_nb_ca15_rams_control {
+ /* [0x0] */
+ uint32_t rf_0;
+ /* [0x4] */
+ uint32_t rf_1;
+ /* [0x8] */
+ uint32_t rf_2;
+ uint32_t rsrvd;
+};
+struct al_nb_semaphores {
+ /* [0x0] This configuration is only sampled during reset of the processor */
+ uint32_t lockn;
+};
+struct al_nb_debug {
+ /* [0x0] */
+ uint32_t ca15_outputs_1;
+ /* [0x4] */
+ uint32_t ca15_outputs_2;
+ uint32_t rsrvd_0[2];
+ /* [0x10] */
+ uint32_t cpu_msg[4];
+ /* [0x20] */
+ uint32_t rsv0_config;
+ /* [0x24] */
+ uint32_t rsv1_config;
+ uint32_t rsrvd_1[2];
+ /* [0x30] */
+ uint32_t rsv0_status;
+ /* [0x34] */
+ uint32_t rsv1_status;
+ uint32_t rsrvd_2[2];
+ /* [0x40] */
+ uint32_t ddrc;
+ /* [0x44] */
+ uint32_t ddrc_phy_smode_control;
+ /* [0x48] */
+ uint32_t ddrc_phy_smode_status;
+ uint32_t rsrvd_3[5];
+ /* [0x60] */
+ uint32_t pmc;
+ uint32_t rsrvd_4[3];
+ /* [0x70] */
+ uint32_t cpus_general;
+ /* [0x74] */
+ uint32_t cpus_general_1;
+ uint32_t rsrvd_5[2];
+ /* [0x80] */
+ uint32_t cpus_int_out;
+ uint32_t rsrvd_6[3];
+ /* [0x90] */
+ uint32_t latch_pc_req;
+ uint32_t rsrvd_7;
+ /* [0x98] */
+ uint32_t latch_pc_low;
+ /* [0x9c] */
+ uint32_t latch_pc_high;
+ uint32_t rsrvd_8[24];
+ /* [0x100] */
+ uint32_t track_dump_ctrl;
+ /* [0x104] */
+ uint32_t track_dump_rdata_0;
+ /* [0x108] */
+ uint32_t track_dump_rdata_1;
+ uint32_t rsrvd_9[5];
+ /* [0x120] */
+ uint32_t track_events;
+ uint32_t rsrvd_10[3];
+ /* [0x130] */
+ uint32_t pos_track_dump_ctrl;
+ /* [0x134] */
+ uint32_t pos_track_dump_rdata_0;
+ /* [0x138] */
+ uint32_t pos_track_dump_rdata_1;
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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