svn commit: r307907 - head/sys/arm/include

[Andrew Turner]

Author: andrew
Date: Tue Oct 25 13:45:59 2016
New Revision: 307907
URL: https://svnweb.freebsd.org/changeset/base/307907

Log:
  Update the armv6 tlb handling functions to detect if it is running on
  hardware that supports the mp extensions. If so it should use the broadcast
  tlb invalidate instructions as other CPUs or devices may need to know about
  the invalidation.
  
  To simplify the code have the compiler optimise out the else case when not
  builing for Cortex-A8.
  
  Sponsored by:	ABT Systems Ltd
  Differential Revision:	https://reviews.freebsd.org/D8092

Modified:
  head/sys/arm/include/cpu-v6.h

Modified: head/sys/arm/include/cpu-v6.h
==============================================================================
--- head/sys/arm/include/cpu-v6.h	Tue Oct 25 12:58:36 2016	(r307906)
+++ head/sys/arm/include/cpu-v6.h	Tue Oct 25 13:45:59 2016	(r307907)
@@ -347,12 +347,21 @@ tlb_flush_range_local(vm_offset_t va, vm
 /* Broadcasting operations. */
 #if __ARM_ARCH >= 7 && defined SMP
 
+#if defined(CPU_CORTEXA8)
+#define	ARM_HAVE_MP_EXTENSIONS	(cpuinfo.mp_ext != 0)
+#else
+#define	ARM_HAVE_MP_EXTENSIONS	1
+#endif
+
 static __inline void
 tlb_flush_all(void)
 {
 
 	dsb();
-	_CP15_TLBIALLIS();
+	if (ARM_HAVE_MP_EXTENSIONS)
+		_CP15_TLBIALLIS();
+	else
+		_CP15_TLBIALL();
 	dsb();
 }
 
@@ -361,7 +370,10 @@ tlb_flush_all_ng(void)
 {
 
 	dsb();
-	_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
+	if (ARM_HAVE_MP_EXTENSIONS)
+		_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIASID(CPU_ASID_KERNEL);
 	dsb();
 }
 
@@ -372,7 +384,10 @@ tlb_flush(vm_offset_t va)
 	KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 
 	dsb();
-	_CP15_TLBIMVAAIS(va);
+	if (ARM_HAVE_MP_EXTENSIONS)
+		_CP15_TLBIMVAAIS(va);
+	else
+		_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 	dsb();
 }
 
@@ -386,8 +401,13 @@ tlb_flush_range(vm_offset_t va,  vm_size
 	    size));
 
 	dsb();
-	for (; va < eva; va += PAGE_SIZE)
-		_CP15_TLBIMVAAIS(va);
+	if (ARM_HAVE_MP_EXTENSIONS) {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVAAIS(va);
+	} else {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	}
 	dsb();
 }
 #else /* SMP */
@@ -411,19 +431,23 @@ icache_sync(vm_offset_t va, vm_size_t si
 
 	dsb();
 	va &= ~cpuinfo.dcache_line_mask;
-	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
+	if (ARM_HAVE_MP_EXTENSIONS) {
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAU(va);
+	} else
 #endif
+	{
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (ARM_HAVE_MP_EXTENSIONS)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -433,10 +457,11 @@ static __inline void
 icache_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (ARM_HAVE_MP_EXTENSIONS)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -446,10 +471,11 @@ static __inline void
 bpb_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_BPIALLIS();
-#else
-	_CP15_BPIALL();
+	if (ARM_HAVE_MP_EXTENSIONS)
+		_CP15_BPIALLIS();
+	else
 #endif
+		_CP15_BPIALL();
 	dsb();
 	isb();
 }
@@ -462,12 +488,15 @@ dcache_wb_pou(vm_offset_t va, vm_size_t 
 
 	dsb();
 	va &= ~cpuinfo.dcache_line_mask;
-	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
+	if (ARM_HAVE_MP_EXTENSIONS) {
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAU(va);
+	} else
 #endif
+	{
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 }